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DLL Control Register
The
register holds the programmable parameters associated with the DLLs within the DMC PHY.
DMC_DLLCTL
DATACYC (R/W)
Data Cycles
Figure 10-5: DMC_DLLCTL Register Diagram
Table 10-14: DMC_DLLCTL Register Fields
Bit No.
(Access)
11:8
DATACYC
(R/W)
7:0
DLLCALRDCNT
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
1
31
30
29
28
27
26
25
0
0
0
0
0
0
Bit Name
Data Cycles.
The DMC_DLLCTL.DATACYC bits select the latency after which the DMC reads da-
ta from the PHY. This field must be written with the value (9). All other values are
reserved.
Taking round trip delay into account, the DLL indicates whether a latency of 2 cycles
is supported by means of status bits.
DLL Calibration RD Count.
The DMC_DLLCTL.DLLCALRDCNT field selects the number of read operations that
the PHY uses for DLL calibration.
9
8
7
6
5
4
3
2
0
1
0
1
0
0
1
0
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x DMC Register Descriptions
1
0
1
1
DLLCALRDCNT (R/W)
DLL Calibration RD Count
16
0
0
10–31
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