Analog Devices ADSP-SC58 Series Hardware Reference Manual page 492

Figure 11-5: Fast Asynchronous SRAM Writes
Asynchronous SRAM Reads with ARDY
The Asynchronous SRAM Read with ARDY figure shows an extended asynchronous SRAM read bus cycle with
SMC_ARDY enabled.
Figure 11-6: Asynchronous SRAM Read with ARDY
SCLK in the Asynchronous SRAM Read with ARDY figure is SCLK0_0.
NOTE:
The programmed SMC bank control parameters are:
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
CLKOUT
SMC_An
SMC_AMSn
SMC_AOE
SMC_ABE1-0
SMC_AWE
SMC_D15-0
WD0
Setup
3 Cycles
SCLK
CLKOUT
SMC_An
SMC_AMSn
SMC_AOE
SMC_ARE
SMC_ARDY
SMC_D15
Pre
Setup
1 Cycle
Setup Write Access
1 Cycle 2 Cycles
A0 A0 + 1 A0 + 2
01 00 00
WD1 WD2
ARDY
Latched in
SCLK
Ready
Sampled
A0
Read Access Extended
Access 5 Cycles
6 Cycles
SMC Programmable Timing Characteristics
Trans. TURN
2 Cycles
A0 + 3
10
WD3
Data
Latched
SCLK to CLKOUT
reference edge
delay
D0
Hold
2 Cycles
11–11