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Resetting a SHARC+ Core Through Another Core
• CCR0 − SHARC0 core reset request bit in shared variable
• IDLE0 − SHARC0 IDLE acknowledgement bit in shared variable
• CCR1 − SHARC1 core reset request bit in shared variable
• IDLE1 − SHARC1 IDLE acknowledgement bit in shared variable
Use the following programming to reset the SHARC+ core.
1. The master core checks the IDLE status bits in shared variable for the corresponding SHARC+ core
(RCU_MSG.C1IDLE and RCU_MSG.C0IDLE).
2. If one of the core idle bits is set then the program jumps to step 10. Otherwise the process continues to step 3.
3. The master core sets the CCRx bit in message register and raises the SOFT0 software interrupt through the
SEC to the SHARC+ core (see
4. The SHARC+ core goes to into the ISR, and checks the "CCRx" status bit in RCU_MSG register to ensure
that software interrupt is for core reset.
ADDITIONAL INFORMATION: The SOFT0 software interrupt handler can be used for other non-reset/
general purposes as well.
ADDITIONAL INFORMATION: The ISR should be in L1 memory.
5. The core should disable all interrupts before entering IDLE for reset.
6. The core sets the appropriate idle status bit (RCU_MSG.C1IDLE and RCU_MSG.C0IDLE).
7. Core enters IDLE.
8. Master core polls for the IDLEx status bit
9. The master core keeps a timeout option where if within N number of cycles the SHARC core doesn't respond
then a system reset is initiated.
ADDITIONAL INFORMATION: N can be decided by the user depending on timing criticality of the applica-
tion.
10. Once the IDLEx status bit is found set, the master core initiates a core reset though the RCU.
11. Clear the RCU_CRSTAT.CR[n] bit.
12. Set the RCU_SIDIS.SI[n] bit to disable the interfaces for core n, to stop DMA accesses to its L1, to stop
accesses to memory for core n, and stop accesses to MMRs.
13. Test the RCU_SISTAT.SI[n] bit to detect when accesses to core n have been disabled and all the pending
transactions have completed.
14. Set the RCU_CRCTL.CR[n] bit to reset core n.
6–6
Programming Examples
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
for more information).
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