Analog Devices ADSP-SC58 Series Hardware Reference Manual page 52

System Status Register ........................................................................................................................... 28–62
MediaLB 6-pin Control 0 Register ........................................................................................................ 28–64
PCI Express
PCIe Features .............................................................................................................................................. 29–2
Functional Description ................................................................................................................................ 29–3
ADSP-SC58x PCIE Register List ............................................................................................................. 29–3
ADSP-SC58x PCIE Interrupt List ......................................................................................................... 29–10
ADSP-SC58x PCIE Trigger List............................................................................................................. 29–10
Definitions ............................................................................................................................................. 29–10
Top-level Block Diagram and Description .............................................................................................. 29–12
Module-level Block Diagrams and Descriptions ..................................................................................... 29–13
Reset Clock and PHY Control Module (RSCKPHY) .......................................................................... 29–14
Responding to a Warm or Hot Reset................................................................................................ 29–15
Application Module (APP) .................................................................................................................. 29–18
Architectural Concepts ........................................................................................................................... 29–20
Register Accesses (PCIe Link and SCB DBI Port) ............................................................................... 29–20
SOC Address Space Accesses ............................................................................................................... 29–21
PCIe Address Space Accesses .............................................................................................................. 29–21
Message Signaled Interrupts (MSI) Controller .................................................................................... 29–23
Internal Address Translation (iATU) ................................................................................................... 29–25
Embedded DMA Controller (eDMA) ................................................................................................. 29–27
Operations................................................................................................................................................. 29–29
Initialization ........................................................................................................................................... 29–29
Port Configuration .............................................................................................................................. 29–29
BARs Disable Example........................................................................................................................ 29–30
Link Training and Establishment ........................................................................................................ 29–31
Downstream Device Enumeration by Root Complex .......................................................................... 29–32
Host Software Writes to Bus Master Enable (BME), Memory Space Enable (MSE), and I/O Space Enable
(ISE) Bits in PCI-Compatible Command Register........................................................................ 29–32
Configuration for Memory Read and Write Transactions ....................................................................... 29–32
lii ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference