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DMA Rx Descriptor Current Register ................................................................................................. 31–143
DMA Rx Interrupt Watch Dog Register .............................................................................................. 31–144
DMA Rx Poll Demand register ............................................................................................................ 31–145
DMA Status Register ........................................................................................................................... 31–146
DMA Tx Buffer Current Register ........................................................................................................ 31–151
DMA Tx Descriptor List Address Register .......................................................................................... 31–152
DMA Tx Descriptor Current Register ................................................................................................. 31–153
DMA Tx Poll Demand Register .......................................................................................................... 31–154
DMA Bus Mode Register .................................................................................................................... 31–155
Channel 1 Credit Shaping Control Register ........................................................................................ 31–158
Channel 1 Average Traffic Transmitted Register .................................................................................. 31–159
Channel 1 High Credit Value Register ................................................................................................. 31–160
Channel 1 Idle Slope Credit Value Register ......................................................................................... 31–161
Channel 1 Low Credit Value Register .................................................................................................. 31–162
Channel 1 Control Bits for Slot Function Register .............................................................................. 31–163
Channel 1 Send Slope Credit Value Register ........................................................................................ 31–164
DMA Interrupt Enable Register .......................................................................................................... 31–165
DMA Missed Frame Register ............................................................................................................... 31–168
DMA Operation Mode Register .......................................................................................................... 31–169
DMA Rx Buffer Current Register ........................................................................................................ 31–173
DMA Rx Descriptor List Address Register ........................................................................................... 31–174
DMA Rx Descriptor Current Register ................................................................................................. 31–175
DMA Rx Interrupt Watch Dog Register .............................................................................................. 31–176
DMA Rx Poll Demand Register .......................................................................................................... 31–177
DMA Status Register ........................................................................................................................... 31–178
DMA Tx Buffer Current Register ........................................................................................................ 31–183
DMA Tx Descriptor List Address Register .......................................................................................... 31–184
DMA Tx Descriptor Current Register ................................................................................................. 31–185
DMA Tx Poll Demand Register .......................................................................................................... 31–186
DMA Bus Mode Register .................................................................................................................... 31–187
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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