Analog Devices ADSP-SC58 Series Hardware Reference Manual page 479

Sharc+ processor
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PHY Control 2 Register
The
DMC_PHY_CTL2
guidelines for proper operation of the DMC.
VALUE[31:16] (R/W)
32 Bit Value
Figure 10-32: DMC_PHY_CTL2 Register Diagram
Table 10-42: DMC_PHY_CTL2 Register Fields
Bit No.
(Access)
31:0
VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register controls programmable PHY features. Program this register as per the programming
15
0
VALUE[15:0] (R/W)
32 Bit Value
31
0
Bit Name
32 Bit Value.
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x DMC Register Descriptions
6
5
4
3
2
1
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
10–73

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