Analog Devices ADSP-SC58 Series Hardware Reference Manual page 513

ADSP-SC58x SMC Register Descriptions
Table 11-8: SMC_B1TIM Register Fields (Continued)
Bit No.
(Access)
18:16 RST
(R/W)
13:8 WAT
(R/W)
6:4 WHT
(R/W)
2:0 WST
(R/W)
11–32
Bit Name
Read Setup Time.
The SMC_B1TIM.RST bits select the setup time (in SCLK0_0 cycles) that the SMC
asserts the SMC_AOE pin before asserting the SMC_ARE pin for an access. The setup
time is from 1 to 8 SCLK0_0 cycles.
Write Access Time.
The SMC_B1TIM.WAT bits select the access time (in SCLK0_0 cycles) that the SMC
asserts the SMC_AWE pin for a write access. The access time is from 1 to 63 SCLK0_0
cycles.
Write Hold Time.
The SMC_B1TIM.WHT bits select the hold time (in SCLK0_0 cycles) that the SMC
waits after de-asserting the SMC_AWE pin before de-asserting the SMC_AOE pin for
the current access. The hold time is from 0 to 7 SCLK0_0 cycles.
Write Setup Time.
The SMC_B1TIM.WST bits select the setup time (in SCLK0_0 cycles) that the SMC
asserts the SMC_AOE pin before asserting the SMC_AWE pin for a write access. The
setup time is from 1 to 8 SCLK0_0 cycles.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 8 SCLK0_0 clock cycles
1 1 SCLK0_0 clock cycle
7 7 SCLK0_0 clock cycles
0 Not supported
1 1 SCLK0_0 clock cycle
63 63 SCLK0_0 clock cycles
0 0 SCLK0_0 clock cycles
1 1 SCLK0_0 clock cycle
7 7 SCLK0_0 clock cycles
0 8 SCLK0_0 clock cycles
1 1 SCLK0_0 clock cycle
7 7 SCLK0_0 clock cycles