Analog Devices ADSP-SC58 Series Hardware Reference Manual page 453

Table 10-22: DMC_MR1 Register Fields (Continued)
Bit No.
(Access)
9 RTT2
(R/W)
6 RTT1
(R/W)
5 DIC1
(R/W)
4:3 AL
(R/W)
2 RTT0
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Rtt_nom.
The DMC_MR1.RTT2 bit is used in conjunction with the DMC_MR1.RTT0 and
DMC_MR1.RTT1 bits.
(9 6 2)
0 0 0 Rtt_Nom disabled
0 0 1 RZQ/4
0 1 0 RZQ/2
0 1 1 RZQ/6
1 0 0 RZQ/12 (reserved if Rtt_Nom is used during writes)
1 0 1 RZQ/8 (reserved if Rtt_Nom is used during writes)
1 1 0 Reserved
1 1 1 Reserved
Rtt_nom.
The DMC_MR1.RTT1 bit combines with the DMC_MR1.RTT0 bit to set the termi-
nation resistance. See the DMC_MR1.RTT2 and DMC_MR1.RTT0 bit description for
more information.
Output Driver Impedance Control.
The DMC_MR1.DIC1 bit is used in conjunction with the DMC_MR1.DIC0 bit.
(5, 1)
0 0 RZQ/6
0 1 RZQ/7
1 0 Reserved
1 1 Reserved
Additive Latency.
The DMC_MR1.AL bits select a number of added latency time for CAS operations in
terms of clock cycles (t
sheet for the SDRAM being used in your system.
Rtt_nom.
The DMC_MR1.RTT0 bit combines with the DMC_MR1.RTT1 and
DMC_MR1.RTT1 bits to set the termination resistance. See the DMC_MR1.RTT1
and DMC_MR1.RTT2 bit descriptions for more information.
ADSP-SC58x DMC Register Descriptions
Description/Enumeration
). For more information about this operation, see the data
CK
0 AL disabled
1 CL-1
2 CL-2
3 Reserved
10–47