Analog Devices ADSP-SC58 Series Hardware Reference Manual page 646

ADSP-SC58x PINT Register Descriptions
Table 14-28: PINT_EDGE_CLR Register Fields
Bit No.
(Access)
31 PIQ31
(R/W1C)
30 PIQ30
(R/W1C)
29 PIQ29
(R/W1C)
28 PIQ28
(R/W1C)
27 PIQ27
(R/W1C)
26 PIQ26
(R/W1C)
25 PIQ25
(R/W1C)
24 PIQ24
(R/W1C)
23 PIQ23
(R/W1C)
22 PIQ22
(R/W1C)
21 PIQ21
(R/W1C)
20 PIQ20
(R/W1C)
19 PIQ19
(R/W1C)
18 PIQ18
(R/W1C)
17 PIQ17
(R/W1C)
16 PIQ16
(R/W1C)
14–74
Bit Name
Pin Interrupt 31 Level.
Set the PINT_EDGE_CLR.PIQ31 bit to enable level sensitivity.
Pin Interrupt 30 Level.
Set the PINT_EDGE_CLR.PIQ30 bit to enable level sensitivity.
Pin Interrupt 29 Level.
Set the PINT_EDGE_CLR.PIQ29 bit to enable level sensitivity.
Pin Interrupt 28 Level.
Set the PINT_EDGE_CLR.PIQ28 bit to enable level sensitivity.
Pin Interrupt 27 Level.
Set the PINT_EDGE_CLR.PIQ27 bit to enable level sensitivity.
Pin Interrupt 26 Level.
Set the PINT_EDGE_CLR.PIQ26 bit to enable level sensitivity.
Pin Interrupt 25 Level.
Set the PINT_EDGE_CLR.PIQ25 bit to enable level sensitivity.
Pin Interrupt 24 Level.
Set the PINT_EDGE_CLR.PIQ24 bit to enable level sensitivity.
Pin Interrupt 23 Level.
Set the PINT_EDGE_CLR.PIQ23 bit to enable level sensitivity.
Pin Interrupt 22 Level.
Set the PINT_EDGE_CLR.PIQ22 bit to enable level sensitivity.
Pin Interrupt 21 Level.
Set the PINT_EDGE_CLR.PIQ21 bit to enable level sensitivity.
Pin Interrupt 20 Level.
Set the PINT_EDGE_CLR.PIQ20 bit to enable level sensitivity.
Pin Interrupt 19 Level.
Set the PINT_EDGE_CLR.PIQ19 bit to enable level sensitivity.
Pin Interrupt 18 Level.
Set the PINT_EDGE_CLR.PIQ18 bit to enable level sensitivity.
Pin Interrupt 17 Level.
Set the PINT_EDGE_CLR.PIQ17 bit to enable level sensitivity.
Pin Interrupt 16 Level.
Set the PINT_EDGE_CLR.PIQ16 bit to enable level sensitivity.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration