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SMPU Status and Error Signals
If a second memory access violation occurs while the SMPU_STAT.IRQ bit is set, the SMPU_STAT.IOVR (inter-
rupt overrun) bit is set. The
SMPU_STAT.IRQ bit is cleared. Any information on the subsequent interrupt is lost. Once the
SMPU_STAT.IRQ bit and the SMPU_STAT.IOVR bit are cleared, any new memory access violations can trigger
an interrupt and its details can be captured.
NOTE:
When a blocked access occurs, the SMPU triggers an interrupt when interrupt generation is enabled. The
SMPU can also be configured to generate a bus error that propagates back to the system master. The sys-
tem master can also trigger an interrupt due to this bus error.
NOTE:
On the processor, each SMPU instance has an interrupt. All of the SMPU interrupts are OR'ed and map-
ped to a single SMPU interrupt on the SEC/GIC. While servicing the SMPU interrupt, check all of the
SMPU_STAT
SMPU_STAT.IRQ bit of the all of the
SMPU Status and Error Signals
If bus errors are enabled (SMPU_CTL.PBEDIS =0), the SMPU generates and returns a bus error to the master
initiating the blocked access. This bit also sets the SMPU_STAT.BERR bit. The
SMPU_BDTLS
registers can be read to get the address and details of the transaction that caused the SMPU to gener-
ate the error.
Write errors are prioritized over read errors.
A bus error status is returned to the system master if:
• an ID-based violation happened and the SMPU_CTL.PBEDIS bit =0
If a second memory access violation occurs while the SMPU_STAT.BERR bit is set, the SMPU_STAT.BEOVR bit
(bus error overrun) is set. The
SMPU_STAT.IRQ bit is cleared. The information about the transaction that caused the SMPU_STAT.BEOVR bit
to be set is lost.
If both the protection violation interrupt is not enabled (SMPU_CTL.PINTEN =0) and the protection
NOTE:
bus error is disabled (SMPU_CTL.PBEDIS =1), the SMPU blocks invalid transactions. However, it does
not provide any status or interrupt information indicating that a transaction is blocked.
SMPU Programming Example
The following example corresponds to using SMPU1 to protect M4 SRAM from MDMA write accesses. In the ex-
ample the region configured for protection is 4KB at the start of M4 SRAM Bank A.
1. Enable SMPU1 interrupts by writing to the
2. Define the memory region to be protected by writing to the
13–12
and the
SMPU_IADDR
registers to determine which triggered the interrupt. The interrupt service routine clears the
SMPU_BADDR
and the
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers are not updated until the
SMPU_IDTLS
SMPU_STAT
registers for which the interrupt is triggered.
SMPU_BDTLS
registers are not updated until the
SMPU_CTL
register.
SMPU_RADDR[n]
and
SMPU_BADDR
register.
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