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In a multidrop bus (MDB) network, for example, an address bit enhances the UART frame. The address bit is inser-
ted between the data bits and the optional parity bit. To configure the UART for MDB mode, set the mode of
operation bits (UART_CTL.MOD [5:4]) to 01.
By convention, the address bit is transmitted low for regular data bytes. When set, it marks special address bytes that
require the attention of all nodes on the network.
Figure 17-6: UART Frame with Address Bit
All transmit operations are processed through the transmit buffer register (UART_THR), so all DMA data transmis-
sions clear the address bit. If data is written to the transmit address or insert pulse register (UART_TAIP) instead,
the same transmit operation is initiated with the only exception that the address bit is sent high.
The UART uses the UART_STAT.ADDR bit of the receiver to signal whether the previously received frame had the
address bit set or not. Hardware updates it every time a new frame is received. When the enable address word inter-
rupt bit (UART_IMSK.EAWI) is set, the reception of an address byte triggers a special status interrupt request.
The address sticky bit (UART_STAT.ASTKY) is the sticky version of the UART_STAT.ADDR bit. Hardware sets
it whenever the UART_STAT.ADDR bit is set. Software can clear the UART_STAT.ASTKY bit with a W1C oper-
ation.
In MDB mode, only address bytes progress to the receive FIFO by default. Data bytes are gated unless the
UART_STAT.ASTKY bit is set. The receiver ignores all traffic on the UART bus. This way, the processor can go
into low-power mode and interrupt activity does not load the processor every time a frame is transmitted on the
UART bus. If, however, an address frame is transmitted, the receiver immediately samples all further traffic. A soft-
ware routine can analyze the received data, decide whether it was of relevance for the local network node, and W1C
the UART_STAT.ASTKY bit if it was not.
Software can overrule of the hardware address frame detection by setting the UART_STAT.ADDR bit and (indirect-
ly) the UART_STAT.ASTKY bit with a W1S operation.
The MDB mode follows an asynchronous serial communication protocol with the following options.
• 1 start bit
• 5–8 data bits
• Address bit
• None, even, odd or sticky parity
• 1, 1½, or 2 stop bits (1½ stop bits are valid only in 5-bit word length)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DATA BITS (0x53)
S
D0
D1
D2
D3
START
BIT
D4
D5
D6
D7
A
P
ADDRESS
BIT
PARITY BIT (OPTIONAL,
INCLUDES ADDRESS BIT)
UART Operating Modes
STOP BIT(S)
17–11
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