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Channel Timing Control Unit
Figure 19-14: Four SR Mode Types, Active High PWM Output Signals
Switching Dead Time (PWM_DT) Register
The second important parameter that must be set up in the initial configuration of the PWM controller is the
switching dead time. Dead time is a short delay introduced between turning off one PWM signal (for example, AH)
and turning on the complementary signal (for example, AL). This short time delay permits turning off a power
switch (AH in this case) to completely recover its blocking capability before the complementary switch is turned on.
This time delay prevents a potentially destructive short-circuit condition from developing across the DC link capaci-
tor of a typical voltage source inverter.
The 10-bit, read/write channel A through channel D dead-time registers
control the dead time for channel-x. If the value carried by any dead-time register is PWMDT, the dead time, Td,
for that channel is:
T
= PWM_CH[x]_DT × 2 × t
d
Therefore, a dead-time value of 0x00A introduces a 200-ns delay (for an SCLK0_0 of 100 MHz). The delay occurs
between turning off any PWM signal (for example, AH) and then turning on its complementary signal (for exam-
ple, AL). The length of dead time can be programmed in increments of 2 × t
100 MHz). The channel A through channel D dead-time registers have a maximum value of 0x3FF (1023 decimal)
and correspond to a maximum programmed dead time of:
T
= 1023 × 2 × t
d(max)
SCLK0_0
Write 0 to the
PWM_CHA_DT
Duty Cycle with Dead Time Control: Calculations for PULSEMODE 00
The duty cycle registers are scaled so that a value of 0 represents a 50% PWM duty cycle. The switching signals
produced are also adjusted to incorporate the programmed dead-time value using the channel dead-time registers
19–20
+PWM_TM/2
0
COUNT
PWM_AH0 1
PWM_AH
HARD
CHOP
PWM_AL0 1
PWM_AL
PWM_AH0 1
PWM_AH
ALTER-
NATE
CHOP
PWM_AL0 1
PWM_AL
PWM_AH0 1
PWM_AH
SOFT
CHOP-
BOTTOM
ON
PWM_AL
PWM_AH
SOFT
CHOP-
TOP
ON
PWM_AL0 1
PWM_AL
PWM_TM 1
SCLK0_0
-9
= 1023 × 2 × 10 × 10
through
PWM_CHD_DT
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
-PWM_TM/2
0
PWM_AH0 2
PWM_AL0 2
PWM_AH0 2
PWM_AL0 2
PWM_AH0 2
PWM_AL0 2
PWM_TM 2
(PWM_CHA_DT
SCLK0_0
= 20.5 µs for an f
SCLK0_0
registers to program the dead time.
+PWM_TM/2
through PWM_CHD_DT)
(or 20 ns for an SCLK0_0 of
rate of 100 MHz.
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