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EPPI Operating Modes
GP 3 FS mode is similar in operation to GP 2 FS mode. However, the start of frame synchronization in GP 3 FS
also considers the state of the EPPI_FS3 pin. All the windowing register settings (EPPI_FRAME, EPPI_LINE,
EPPI_HDLY, EPPI_HCNT, EPPI_VDLY, and
and error generation are the same as for GP 2 FS mode. In addition, for GP 3 FS mode with internal frame syncs,
the EPPI_CTL.FLDSEL bit setting specifies the condition under which the transfer begins.
The EPPI generates the EPPI_FS3 signal and toggles during every assertion of EPPI_FS2 or a combination of
EPPI_FS2 and EPPI_FS1. The toggle depends on the EPPI_CTL.FLDSEL bit setting. The EPPI skips an
EPPI_FS2 signal when the EPPI_FS3 value is high. Because of this condition, program the EPPI_FS2 period
value to half of the total number of pixels in the frame as in GP 3 FS mode. When in GP 2 FS mode, program the
EPPI_FS2 period with the value equal to the number of pixels per frame.
Supported Data Formats
The following sections describe EPPI receive and transmit data formats.
Receive Data Formats
The EPPI Receive Data Formats table provides information about EPPI configuration for specific use models for
receive data.
Table 18-11: EPPI Receive Data Formats
Input Data Width
Use Model
8
NTSC/PAL data
RGB sensor
ADCs
18–22
registers), as well as data reception or transmission
EPPI_VCNT
Splitting/Packing Options
EPPI_CTL.SPLTEO =1
EPPI_CTL.SUBSPLTODD =1 if necessary to separate chroma compo-
nents
No splitting possible.
EPPI_CTL.PACKEN =1 – Four EPPI words are packed to 32-bit DMA
data.
EPPI_CTL.PACKEN =0 – Each EPPI word is sent as 8-bit data on the
32-bit DMA bus. This transfer consumes 4 times the DMA bandwidth of
the 8-bit case with EPPI_CTL.PACKEN =1;
Gives I (in phase) and Q (quadrature) components.
EPPI_CTL.SPLTEO =1
EPPI_CTL.SUBSPLTODD =0 since there are only two components.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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