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L2 System Memory Event Control
• Applies an ECC algorithm to the two 32-bit words
• Writes the corrected data back to memory
While the atomic refresh operation is ongoing, other accesses to the same SRAM bank are locked-out. The
L2CTL_STAT.RFRS status bit signals an ongoing refresh operation. Hardware clears the bit after the operation
has finished. The content of the
In safety-critical applications, software can refresh all L2 SRAM by periodically writing to the
with values. It increments with a value of eight until all SRAM locations are refreshed.
Memory refresh operation is meaningless when the L2CTL_CTL.BK0EDIS through L2CTL_CTL.BK7EDIS
disable bits are set.
L2 System Memory Event Control
The following sections describe event control features of the L2 system memory, such as error response.
ECC Error Interrupt
A bus error is signaled under any of the following conditions.
• A write access to ROM address space
• A read/write access to reserved address space
• An ECC multi-bit error in an ECC-enabled bank. A non-modulo, 32-bit write to an ECC-enabled bank can
also potentially create a bus error response due to an ECC multi-bit error. This response is because the L2 sys-
tem memory implements a 32-bit ECC, and therefore a non-modulo, 32-bit write results in a read. This read
can create multi-bit errors even if the memory was initialized.
Bus error notifications are stored in the
en port are stored in the
ed in the
L2CTL_ET0/L2CTL_ET1
ADSP-SC58x L2CTL Register Descriptions
L2 Memory Controller (L2CTL) contains the following registers.
Table 9-5: ADSP-SC58x L2CTL Register List
Name
L2CTL_CTL
L2CTL_EADDR0
L2CTL_EADDR1
L2CTL_ERRADDR0
9–10
L2CTL_RFA
register must not change while the refresh operation is ongoing.
L2CTL_STAT
L2CTL_EADDR0/L2CTL_EADDR1
register of the port.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register, and the addresses that generated the error on a giv-
register of that port. The details of the error are stor-
Description
Control Register
Error Type 0 Address Register
Error Type 1 Address Register
ECC Error Address 0 Register
L2CTL_RFA
register
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