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Peripherals
Figure 1-31: USB System Diagram
Media Local Bus (6-pin) (MLB)
The
Media Local Bus (MLB)
sumes familiarity with these standards. For more information, refer to the Media Local Bus specification version 4.2.
Figure 1-32: MLB System Diagram
PCI Express
PCI Express
is a high performance, general purpose I/O interconnect defined for a wide variety of computing and
communication platforms.
Figure 1-33: PCIE System Diagram
Housekeeping ADC (HADC)
The
Housekeeping ADC (HADC)
from single supply and features throughput rates up to 1 MSPS. The HADC can be used for the collection of
housekeeping parameters like voltages, temperatures in the system or for any general-purpose use as well.
1–16
Differential Data Pins (USB_DM/DP)
OTG Host/Device Pin (USB_ID)
VBUS Control Pin (USB_VBC)
USB_CLKIN Pin
Clocked by SYSCLK_0
supports the MOST25, MOST50 and MOST150 standards and this document as-
PB_04 Pin
MLB0_CLK
PB_05 Pin
MLB0_SIG
PB_06 Pin
MLB0_DAT
PD_14 Pin
MLB0_CLKOUT
Clocked by SCLK_0
Differential TX Data Pins (PCIE_TXP/M)
Differential RX Data Pins (PCIE_RXP/M)
Reference Resistor Pin (PCIE_REF)
Clocked by SYSCLK_0
is a 12-bit (with 10-bit accuracy), successive approximation ADC. It operates
USB
USB DMA Complete Interrupts to SEC/GIC
USB Status Interrupts to SEC/GIC
USB Status Triggers to TRU Slaves
System MMR Write-Protection (WP154:153) from SPU
Enable Secure Peripheral (SECUREP154:153) from SPU
MLB
MLB Channel Interrupts (MLB0_INT1:0) to SEC/GIC
MLB Status Interrupt (MLB0_STAT) to SEC/GIC
System MMR Write-Protection (WP143) from SPU
Enable Secure Peripheral (SECUREP143) from SPU
PCIE
PCIe Reset Request Interrupt to SEC/GIC
PCIe DMA Completion Interrupt to SEC/GIC
PCIe Status Interrupt to SEC/GIC
PCIe DMA Completion Trigger to TRU Slaves
System MMR Write-Protection (WP151) from SPU
Enable Secure Peripheral (SECUREP151) from SPU
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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