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OTPC Interrupt Signals
When making 32-bit accesses to OTP memory, a double-bit error in any 16-bit segment triggers the OTPC_INT
interrupt. The OTPC also has the OTPC dual bit error (OTPC0_ERR) with the SEC ID of 5 and the GIC ID of
37. See the
System Event Controller (SEC) and Generic Interrupt Controller (GIC)
OTPC Status and Error Signals
The OTP controller does not produce error signals.
OTP API Overview
The ROM provides a set of functions to facilitate OTP field access. The OTP memory is broken up into a set of
specialized fields that are described in this section. The API removes the requirement of understanding the details of
the layout or OTP access procedures.
All OTP accesses are made through the provided API.
OTP Programming
The OTP programming API provides a simple access, abstracting particulars of the OTP controller.
Any fields that contain zero or null pointers are skipped.
All addresses are assumed to be byte addresses unless otherwise noted.
A list of APIs follows:
bool adi_rom_otp_pgm(otp_data* data);
bool adi_rom_lock();
OTP Program
Program OTP memory using a struct containing the following predefined data fields.
Name
PP Define
Prototype
Argument
Return Value
Stack Requirements
bool res = adi_rom_otp_pgm(data);
The following type of struct is available for programming. Refer to the ROM header file for the exact definition
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
OTP Program
FUNC_ROM_OTPPGM
bool adi_rom_otp_pgm(otp_data* data);
data
bool
valid stack
OTP Program
Lock API
OTPC Event Control
chapter for more information.
-
-
struct containing data to program
OTP with
true for programming success
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12–3
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