Peripherals; General-Purpose I/O (Gpio) Peripherals - Analog Devices ADSP-SC58 Series Hardware Reference Manual

System MMR Write-Protection (WP10-11) from SPU
Enable Secure Peripheral (SECUREP10-11) from SPU
Figure 1-15: CRC System Diagram

Peripherals

The SHARC+ processor contains a rich set of industry leading system peripherals. The processor is the platform of
choice for applications that require RISC-like programmability, multimedia support, and leading edge signal pro-
cessing in one integrated package. These applications span a wide array of markets, including automotive, pro audio,
and industrial-based applications that require high floating-point performance. These peripherals are described in
the following sections.
•

General-Purpose I/O (GPIO) Peripherals

•
DAI/SRU Peripherals
•
Dedicated Pin Peripherals
General-Purpose I/O (GPIO) Peripherals
The SHARC+ processors feature up to 102 general-purpose I/O pins mapped across up to seven ports (PORT A
through PORT G). Each pin can be configured individually to serve as a GPIO pin or as a peripheral-specific pin.
GPIO Ports (PORT)
When configured in the default GPIO mode, the PORT pins allow for the processor to interface to system compo-
nents to provide handshaking functionality as either inputs or outputs. When in output mode, open-drain output is
supported. A single MMR access can be used to sense or set individual pins or a complete port of 16 pins.
Additionally, each GPIO pin can optionally be configured to raise a system interrupt on the processor via a dedicat-
ed pin interrupt (PINT) block, and all peripheral functions are controlled via a set of port multiplexing registers,
with specific settings defined in the processor data sheet.
Figure 1-16: PORT System Diagram
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
CRC Polynomial (CRC_POLY)
Expected Checksum (CRC_COMP)
Automated Reads from Memory
Clocked by SCLK0_0
Clocked by SCLK0_0 from CGU0
System MMR Write-Protection for (WP34-40) from SPU
Enable Secure Peripheral (SECUREP34-40) from SPU
PX_YY Pins (X = A-G, YY = 00-15)
System MMR Write-Protection (WP42-47) from SPU
Enable Secure Peripheral (SECUREP42-47) from SPU
CRC
CRC Datacount Expiration Interrupts to SEC/GIC
CRC Error Interrupts to SEC/GIC
Automated Writes to Memory
PORTx
PX_YY Pins (X = A-G, YY = 00-15)
PINTx_BLOCK Interrupts to SEC/GIC
PINT
PINTx_BLOCK Triggers to TRU
Peripherals
1–9