Analog Devices ADSP-SC58 Series Hardware Reference Manual page 53

Inbound Programming Example (BAR Match Mode) ......................................................................... 29–33
Inbound Programming Example (Address Match Mode)..................................................................... 29–34
Outbound Programming Example ...................................................................................................... 29–35
Non DMA Transfers............................................................................................................................... 29–36
Transmit Transaction Layer Packets (TLP) ......................................................................................... 29–36
Receive Transaction Layer Packets (TLP) ............................................................................................ 29–37
DMA Transfers....................................................................................................................................... 29–37
Read Transfer ...................................................................................................................................... 29–38
Write Transfer ..................................................................................................................................... 29–39
Flow Control .......................................................................................................................................... 29–40
EP to EP Transactions ............................................................................................................................ 29–40
Gen2 5.0 GT/s Operation ...................................................................................................................... 29–40
Power Management ................................................................................................................................ 29–40
Power Management Software .............................................................................................................. 29–40
Active State Power Management (ASPM)............................................................................................ 29–42
Completion Timeout Ranges.................................................................................................................. 29–42
PHY Registers Access ............................................................................................................................. 29–42
RCCKPHY ......................................................................................................................................... 29–42
Event Control ............................................................................................................................................ 29–42
Error Handling and Debug..................................................................................................................... 29–42
System Cross Bar Master Interface to PCIe Link Error Mapping ........................................................ 29–42
PCIe Link Error Mapping to SCB Slave Interface ............................................................................... 29–43
Messages................................................................................................................................................. 29–43
PCIe Interrupts ...................................................................................................................................... 29–43
PCIe Interrupt Request ....................................................................................................................... 29–43
End Point ............................................................................................................................................ 29–47
Root Complex ..................................................................................................................................... 29–47
Local Interrupts................................................................................................................................... 29–49
Reset Interrupt Request .......................................................................................................................... 29–50
DMA Interrupts ..................................................................................................................................... 29–50
Programming Model.................................................................................................................................. 29–50
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference liii