Analog Devices ADSP-SC58 Series Hardware Reference Manual page 174

Table 3-13: CGU_DIV Register Fields (Continued)
Bit No.
(Access)
7:5 S0SEL
(R/W)
4:0 CSEL
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
SCLK 0 Divisor.
The CGU_DIV.S0SEL selects the divisor in the SCLK0 equation:
SCLK0 frequency = (SYSCLK frequency) / CGU_DIV.S0SEL
Where the value of CGU_DIV.S0SEL is between 1 and 7.
CCLK Divisor.
The CGU_DIV.CSEL selects the divisor in the CCLK equation:
CCLK frequency = (SYS_CLKIN frequency / (DF+1)) * MSEL / CGU_DIV.CSEL
Where the value of CGU_DIV.CSEL is between 1 and 31.
ADSP-SC58x CGU Register Descriptions
Description/Enumeration
0 S0SEL = 8
1-7 S0SEL = 1 to 7
0 CSEL = 32
1-31 CSEL= 1 to 31
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