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ADSP-SC58x DMC Register Descriptions
Data Calibration Address Register
The
DMC_DT_CALIB_ADDR
the DMC PHY DLL calibration, a particular set of locations in the DRAM is written and a series of reads are per-
formed back to back to calibrate the PHY. The DMC PHY needs prior information about the data that would be
read during the PHY DLL calibration. The controller performs one burst write operation to the address program-
med in
DMC_DT_CALIB_ADDR
Note: While the exact address chosen does not matter much during memory initialization, if calibration of the PHY
is performed when the DRAM contains valid data, care needs to be taken to ensure that this address points to an
unused address. Else, this operation will modify application data stored at the address selected.
DMC_DT_CALIB_ADDR[15:0] (R/W)
Data calibration address
DMC_DT_CALIB_ADDR[31:16] (R/W)
Data calibration address
Figure 10-6: DMC_DT_CALIB_ADDR Register Diagram
Table 10-15: DMC_DT_CALIB_ADDR Register Fields
Bit No.
(Access)
31:0
DMC_DT_CALIB_ADDR Data calibration address.
(R/W)
10–32
register provides the address used for the data calibration for read and write. During
(0x0090).
Bit Name
The DMC_DT_CALIB_ADDR.DMC_DT_CALIB_ADDR bit field contains the ad-
dress to be programmed for the data calibration for read and write.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Description/Enumeration
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
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