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Software Generated Interrupt Security Register
The
GICDST_SGI_SECURITY
controls whether the corresponding interrupt is in Group 0 or Group 1. Typically, when used with a processor that
implements the ARM Security Extensions, Group 0 interrupts are Secure interrupts, and Group 1 interrupts are
Non-secure interrupts,
Figure 7-63: GICDST_SGI_SECURITY Register Diagram
Table 7-66: GICDST_SGI_SECURITY Register Fields
Bit No.
(Access)
15:0
VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers provide a status bit for each interrupt supported by the GIC. Each bit
15
14
13
0
0
0
VALUE (R/W)
Software Generated Interrupt Security
Bit Name
Software Generated Interrupt Security.
Each bit in the GICDST_SGI_SECURITY.VALUE bit field controls whether the
corresponding interrupt is in Group 0 or Group 1.
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x GICDST Register Descriptions
4
3
2
1
0
0
0
0
0
0
7–97
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