Clocks Divisor Register - Analog Devices ADSP-SC58 Series Hardware Reference Manual

Clocks Divisor Register

The register controls clock divisors for core clocks, system clocks, external (off core) memory clocks, and
CGU_DIV
output clock. Read after write accesses to the
change is still in progress.
S1SEL (R/W)
SCLK 1 Divisor
SYSSEL (R/W)
SYSCLK Divisor
LOCK (R/W)
Lock
UPDT (R/W)
Update Clock Divisors
ALGN (R0/W)
Align
Figure 3-7: CGU_DIV Register Diagram
Table 3-13: CGU_DIV Register Fields
Bit No.
(Access)
31 LOCK
(R/W)
30 UPDT
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
CGU_DIV
15 14 13 12 11 10
0 1 0 0 1
31 30 29 28 27 26
0 0 0 0 0
Bit Name
Lock.
If the global lock bit is set (SPU_CTL.GLCK bit =1) and the CGU_DIV.LOCK bit is
set, the
Update Clock Divisors.
The CGU_DIV.UPDT controls whether the CGU drives new CGU_DIV.CSEL,
CGU_DIV.SYSSEL, CGU_DIV.S0SEL, CGU_DIV.S1SEL, CGU_DIV.DSEL,
and CGU_DIV.OSEL values to PLL after
register returns the new value even if the clock's frequency
9 8 7 6 5 4 3
0 0 0 0 1 0 0 0
25 24 23 22 21 20 19 18
1 0 0 0 0 0 0 1
Description/Enumeration
register is read only (locked).
CGU_DIV
0 Unlock
1 Lock
0 No PLL Update
1 Drive Updated SEL Values to PLL
ADSP-SC58x CGU Register Descriptions
2 1 0
1 0 0
CSEL (R/W)
CCLK Divisor
S0SEL (R/W)
SCLK 0 Divisor
17 16
0 0 0
DSEL (R/W)
DCLK Divisor
OSEL (R/W)
OCLK Divisor
register update.
CGU_DIV
3–21