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SYS_CLKINx
Figure 3-1: CGU PLL Block Diagram (x=0 CGU0, x=1 CGU1)
The SYS_CLKOUT Generation figure is a conceptual representation of the CLKOUT module. Different clocks
that originate from the CGU blocks are available on the SYS_CLKOUT output pin. The selection of the clock out-
put on the SYS_CLKOUT pin is controlled by the CGU_CLKOUTSEL.CLKOUTSEL bit field.
Additional configuration options are configured using the Clock Distribution Unit. See
Options.
Figure 3-2: SYS_CLKOUT Generation
The processor supports two PLLs (CGU1–0), see the CDU Block Diagram figure in the Clock Distribu-
NOTE:
tion (CDU) chapter. The configuration of CGU0 is mandatory because it provides the clock to the chip
infrastructure (Fabric, L2 cache, L2 system, SEC and GIC) and to some high speed peripherals.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DF
Charge Pump/
PFD
/1 or /2
Loop Filter
MSEL
MSEL[6:0]
SYS_CLKIN0
SYS_CLKIN1
SYSCLK_0
CLKO0
CLK02
CLKO3
CLKO5
CLKO7
CLKO8
CSEL[4:0]
CSEL
SYSSEL[4:0]
SSEL
S0SEL[2:0]
VCO
PLLCLK
S0SEL
S1SEL[2:0]
S1SEL
DSEL[4:0]
DSEL
OSEL[6:0]
OSEL
÷2
÷4
SYS_CLKOUT
÷4
÷4
÷4
÷4
÷4
CLKOUTSEL[3:0]
CGU Functional Description
BYPASS
CCLK0EN
CCLK0_x
CCLK1EN
CCLK1_x
SYSCLK_0
SCLK0EN
SCLK0_x
SCLK1EN
SCLK1_x
DCLKEN
DCLK_x
OCLKEN
OCLK_x
CDU Clock Configuration
3–5
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