Analog Devices ADSP-SC58 Series Hardware Reference Manual page 465

Sharc+ processor
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DMC Read Data Buffer Mask Register 1
The
DMC_RDDATABUFMSK1
VALUE[31:16] (R/W)
Mask for Read Data Buffer ID1
Figure 10-22: DMC_RDDATABUFMSK1 Register Diagram
Table 10-31: DMC_RDDATABUFMSK1 Register Fields
Bit No.
(Access)
31:0
VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register bits mask the respective ID bits in the DMC Priority Mask ID register.
15
0
VALUE[15:0] (R/W)
Mask for Read Data Buffer ID1
31
0
Bit Name
Mask for Read Data Buffer ID1.
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x DMC Register Descriptions
6
5
4
3
2
1
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
10–59

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