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Shared Peripheral Interrupt Configuration Register
The
GICDST_SPI_CFG[n]
VALUE[31:16] (R/W)
Shared Peripheral Interrupt Configuration
Figure 7-41: GICDST_SPI_CFG[n] Register Diagram
Table 7-42: GICDST_SPI_CFG[n] Register Fields
Bit No.
(Access)
31:0
VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register provides a 2-bit Int_config field for each interrupt supported by the GIC.
15
0
VALUE[15:0] (R/W)
Shared Peripheral Interrupt Configuration
31
0
Bit Name
Shared Peripheral Interrupt Configuration.
The GICDST_SPI_CFG[n].VALUE bit field identifies whether the corresponding
interrupt is:
edge-triggered or level-sensitive
handled using the 1-N model or using the N-N model
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x GICDST Register Descriptions
6
5
4
3
2
1
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
7–73
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