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Channel 2 Credit Shaping Control Register ........................................................................................ 31–190
Channel 2 Avg Traffic Transmitted Status Register .............................................................................. 31–191
Channel 2 High Credit Value Register ................................................................................................. 31–192
Channel 2 Idle Slope Credit Value Register ......................................................................................... 31–193
Channel 2 Low Credit Value Register .................................................................................................. 31–194
Channel 2 Control Bits for Slot Function Register .............................................................................. 31–195
Channel 2 Send Slope Credit Value Register ........................................................................................ 31–196
DMA Interrupt Enable Register .......................................................................................................... 31–197
DMA Missed Frame Register ............................................................................................................... 31–200
DMA Operation Mode Register .......................................................................................................... 31–201
DMA Rx Buffer Current Register ........................................................................................................ 31–205
DMA Rx Descriptor List Address Register ........................................................................................... 31–206
DMA Rx Descriptor Current Register ................................................................................................. 31–207
DMA Rx Interrupt Watch Dog Register .............................................................................................. 31–208
DMA Rx Poll Demand register ............................................................................................................ 31–209
DMA Status Register ........................................................................................................................... 31–210
DMA Tx Buffer Current Register ........................................................................................................ 31–215
DMA Tx Descriptor List Address Register .......................................................................................... 31–216
DMA Tx Descriptor Current Register ................................................................................................. 31–217
DMA Tx Poll Demand Register .......................................................................................................... 31–218
FLow Control Register ........................................................................................................................ 31–219
RGMII Control and Status Register .................................................................................................... 31–221
Hash Table High Register .................................................................................................................... 31–222
Hash Table Low Register ..................................................................................................................... 31–223
Interrupt Mask Register ....................................................................................................................... 31–224
MMC IPC Rx Interrupt Mask Register ............................................................................................... 31–225
MMC IPC Rx Interrupt Register ........................................................................................................ 31–231
Interrupt Status Register ...................................................................................................................... 31–236
Layer3 and Layer4 Control Register .................................................................................................... 31–238
Layer 3 Address0 Register .................................................................................................................... 31–240
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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