Analog Devices ADSP-SC58 Series Hardware Reference Manual page 495

SMC Programmable Timing Characteristics
NOR_DQ15-0
Figure 11-8: 32-bit Asynchronous Flash Read
Asynchronous Flash Writes
The Asynchronous Flash Write Operation figure shows a single asynchronous flash write bus cycle.
Figure 11-9: Asynchronous Flash Write Operation
For this example, the SMC has been programmed with:
• Pre-setup time = 1 cycle
• Write setup time = 2 cycles
• Write access time = 6 cycles
• Write hold time = 2 cycles
• Pre-access time = 0
The asynchronous flash write bus cycle is again almost identical to the asynchronous SRAM write. The SMC_AWE
pin is connected to flash write enable signal (NOR_WE). However, in asynchronous flash writes the SMC uses the
11–14
CLKOUT
NOR_An
NOR_CE
NOR_ADV
NOR_OE
Setup Read Access
2 Cycles 5 Cycles
CLKOUT
NOR_An
NOR_CE
NOR_ADV
NOR_WE
SMC_ABE1-0
NOR_DQ15-0
Pre
Setup
1 Cycle
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
A0
D0
Hold
2 Cycles
Read Data
Latched Here
A0
00
WD0
Write Write Access
Setup 6 Cycles
2 Cycles
A0 + 1
D1
Read Data
Latched Here
Write
Hold
2 Cycles