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SPI Functional Description
The SPI_STAT.RFE bit defines when the receive buffer can be read, indicating that
SPI_RFIFO
is not empty.
The SPI_STAT.TFF bit defines when the transmit buffer can be written, indicating that the
is not
SPI_TFIFO
full. The end of a single word transfer occurs when the SPI_STAT.RFE bit is cleared. The status indicates that a
new word has been received and written into the receive FIFO. The SPI_STAT.RFE bit remains cleared as long as
the receive FIFO has valid data.
To maintain software compatibility with other SPI devices, the SPI_STAT.SPIF bit is also available for polling.
This bit can have a slightly different behavior from other commercially available devices.
In master mode with the SPI_CTL.ASSEL bit cleared, software manually asserts the required slave select signal
before starting the transaction. After all data transfers, software typically releases the slave select line.
When the receive or transmit word counters are enabled in the
or
registers, the SPI
SPI_TXCTL
SPI_RXCTL
generates a finish interrupt at the end of the transfer. It signals the end of all transfers related to that transaction.
Transmit Operation in Non-DMA Mode
The transmit operation in non-DMA mode is enabled through the SPI_TXCTL.TEN bit. It can be enabled inde-
pendently from the receive operation, and the transmit channel can become the initiating channel based on the
SPI_TXCTL.TTI bit setting.
Transmit underrun is not possible in this mode, as no new transfer initiates unless the transmit FIFO is empty (in
the case that SPI_TXCTL.TTI =1). A receive overflow is detected when data from a new frame transfer replaces
older data in a full receive FIFO. This event can occur if SPI_TXCTL.TTI =1 and the receive channel is enabled
in a non-initiating capacity.
An SPI transmit interrupt request is signaled once the transmit channel has been enabled and the transmit FIFO is
not full. The SPI uses the SPI_TXCTL.TDR bit setting to control the frequency of the interrupt request.
Receive Operation in Non-DMA Mode
The receive operation in non-DMA mode is enabled through the SPI_RXCTL.REN bit. It can be enabled inde-
pendently from the transmit operation, and the receive channel can become the initiating channel based on the
SPI_RXCTL.RTI bit setting.
Receive overflow is not possible in this mode, as no new transfer initiates when the receive FIFO is full (in the case
of SPI_RXCTL.RTI =1). A transmit underrun can occur (SPI_TXCTL.TDU bit) when no valid data is in the
register when a transfer is initiated. This event can occur if SPI_RXCTL.RTI =1 and the transmit
SPI_TFIFO
channel is enabled in a non-initiating capacity.
An SPI receive interrupt request is signaled once the receive channel has been enabled and there is data waiting to be
read. The SPI uses the SPI_RXCTL.RDR bit setting to control the frequency of the interrupt request.
Dual I/O Mode
In Dual I/O mode, the SPI_MISO and SPI_MOSI pins are configured to operate in the same direction which
doubles bandwidth. The SPI uses the SPI_CTL.SOSI bit to determine the order of bits on the pins. When set,
the processor sends the first bit on the SPI_MOSI pin and the second bit on the SPI_MISO pin. If the
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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