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Analog Devices adsp-2100 Manual

Analog Devices adsp-2100 Manual

Adsp-2100 family programmable single-chip microprocessors

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1.1

OVERVIEW ........................................................................................ 1-1

1.1.1

Functional Units ........................................................................... 1-1

1.1.2

Memory And System Interface .................................................. 1-3

1.1.3

Instruction Set .............................................................................. 1-4

1.1.4

DSP Performance ......................................................................... 1-4

1.2

CORE ARCHITECTURE .................................................................. 1-5

1.2.1

Computational Units ................................................................... 1-6

1.2.2

Address Generators & Program Sequencer ............................. 1-7

1.2.3

1.3

ON-CHIP PERIPHERALS ................................................................ 1-8

1.3.1

Serial Ports .................................................................................... 1-8

1.3.2

1.3.3

Host Interface Port ....................................................................... 1-9

1.3.4

DMA Ports .................................................................................... 1-9

1.3.5

Analog Interface ......................................................................... 1-10

1.4

ADSP-2100 FAMILY DEVELOPMENT TOOLS ......................... 1-10

1.5

ORGANIZATION OF THIS MANUAL ....................................... 1-11

2.1

OVERVIEW ........................................................................................ 2-1

2.1.1

Binary String ................................................................................. 2-1

2.1.2

Unsigned ....................................................................................... 2-1

2.1.3

Signed Numbers: Twos-Complement ...................................... 2-1

2.1.4

Fractional Representation: 1.15 .................................................. 2-2

2.1.5

ALU Arithmetic ........................................................................... 2-2

2.1.6

MAC Arithmetic .......................................................................... 2-3

2.1.7

Shifter Arithmetic ........................................................................ 2-3

2.1.8

Summary ....................................................................................... 2-4

2.2

ARITHMETIC/LOGIC UNIT (ALU) .............................................. 2-5

2.2.1

ALU Block Diagram Discussion ................................................ 2-5

2.2.2

Standard Functions...................................................................... 2-7

2.2.3

ALU Input/Output Registers .................................................... 2-8

2.2.4

Multiprecision Capability ........................................................... 2-8

2.2.5

ALU Saturation Mode ................................................................. 2-8

2.2.6

ALU Overflow Latch Mode ....................................................... 2-9

........................................................................................ 1-8

........................................................................................ 1-9

COMPUTATIONAL UNITS

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Page 1: Table Of Contents
1.3.3 Host Interface Port ............... 1–9 1.3.4 DMA Ports ..................1–9 1.3.5 Analog Interface ................. 1–10 ADSP-2100 FAMILY DEVELOPMENT TOOLS ......1–10 ORGANIZATION OF THIS MANUAL ........1–11 CHAPTER 2 COMPUTATIONAL UNITS OVERVIEW ..................2–1 2.1.1 Binary String ................. 2–1 2.1.2...
Page 2 Contents 2.2.7 Division ..................2–9 2.2.8 ALU Status .................. 2–13 MULTIPLIER/ACCUMULATOR (MAC) ........2–13 2.3.1 MAC Block Diagram Discussion ..........2–13 2.3.2 MAC Operations ................ 2–16 2.3.2.1 Standard Functions.............. 2–16 2.3.2.2 Input Formats ............... 2–18 2.3.2.3 MAC Input/Output Registers ........... 2–18 2.3.2.4 MR Register Operation ............
Page 3 Contents STATUS REGISTERS & STATUS STACK ........3–20 3.5.1 Arithmetic Status Register (ASTAT) ........3–20 3.5.2 Stack Status Register (SSTAT) ..........3–21 3.5.3 Mode Status Register (MSTAT) ..........3–22 CONDITIONAL INSTRUCTIONS ..........3–24 TOPPCSTACK ................. 3–25 3.7.1 TOPPCSTACK Restrictions ............3–27 CHAPTER 4 DATA TRANSFER OVERVIEW ..................
Page 4 Contents CONFIGURATION EXAMPLE ............. 5–15 TIMING EXAMPLES ..............5–16 5.10 COMPANDING AND DATA FORMAT ........5–23 5.10.1 Companding Operation Example ........... 5–24 5.10.2 Contention For Companding Hardware ........ 5–25 5.10.3 Companding Internal Data ............5–25 5.11 AUTOBUFFERING................5–26 5.11.1 Autobuffering Control Register ..........5–27 5.11.2 Autobuffering Example ............
Page 5 Contents CHAPTER 7 HOST INTERFACE PORT OVERVIEW ..................7–1 HIP PIN SUMMARY ................. 7–2 HIP FUNCTIONAL DESCRIPTION ..........7–4 HIP OPERATION ................7–6 7.4.1 Polled Operation ................7–7 7.4.1.1 HIP Status Synchronization ..........7–8 7.4.2 Interrupt-Driven Operation ............7–9 7.4.3 HDR Overwrite Mode..............
Page 6 Contents CHAPTER 9 SYSTEM INTERFACE OVERVIEW ..................9–1 CLOCK SIGNALS................9–3 9.2.1 Synchronization Delay ..............9–3 9.2.2 1x & 1/2x Clock Considerations ..........9–4 RESET ..................9–4 SOFTWARE-FORCED REBOOTING ..........9–4 9.4.1 ADSP-2181 Register Values For BDMA Booting ....9–13 EXTERNAL INTERRUPTS .............
Page 7 Contents 10.4 BOOT MEMORY INTERFACE ............ 10–15 10.4.1 Boot Pages ................. 10–15 10.4.2 Powerup Boot & Software Reboot ........10–16 10.4.3 Boot Memory Access ............... 10–17 10.4.4 Boot Loading Sequence ............10–17 10.5 BUS REQUEST/GRANT .............. 10–21 10.6 ADSP-2181 MEMORY INTERFACES ......... 10–23 10.6.1 ADSP-2181 Program Memory Interface .......
Page 8 Contents CHAPTER 12 PROGRAMMING MODEL 12.1 OVERVIEW ..................12–1 12.1.1 Data Address Generators ............12–2 12.1.1.1 Always Initialize L Registers ..........12–2 12.1.2 Program Sequencer ..............12–4 12.1.2.1 Interrupts ................12–4 12.1.2.2 Loop Counts ................. 12–4 12.1.2.3 Status And Mode Bits............12–5 12.1.2.4 Stacks ..................
Page 9 Contents CHAPTER 15 INSTRUCTION SET REFERENCE 15.1 QUICK LIST OF INSTRUCTIONS ..........15–1 15.2 OVERVIEW ..................15–2 15.3 INSTRUCTION TYPES & NOTATION CONVENTIONS ..15–3 15.4 MULTIFUNCTION INSTRUCTIONS .......... 15–4 15.4.1 ALU/MAC With Data & Program Memory Read ....15–4 15.4.2 Data &...
Page 10 Contents Multiply ..................15–43 Multiply/Accumulate ..............15–45 Multiply/Subtract ................. 15–47 Clear ....................15–49 Transfer MR ..................15–50 Conditional MR Saturation ............15–51 SHIFTER Arithmetic Shift ................15–52 Logical Shift ..................15–54 Normalize ..................15–56 Derive Exponent ................15–58 Block Exponent Adjust..............15–60 Arithmetic Shift Immediate ............
Page 11 Contents MISC Stack Control .................. 15–86 Mode Control ................. 15–89 Modify Address Register .............. 15–91 ..................15–92 Interrupt Enable/Disable ............. 15–93 MULTIFUNCTION ALU/MAC/SHIFT Operation with Memory Read ....15–94 ALU/MAC/SHIFT Operation with Register to Register Move . 15–98 ALU/MAC/SHIFT Operation with Memory Write ....15–101 Data &...
Page 12 Contents APPENDIX D INTERRUPT VECTOR ADDRESSES INTERRUPT VECTOR ADDRESSES ..........D–1 APPENDIX E CONTROL/STATUS REGISTERS OVERVIEW ..................E-1 INDEX...
Page 13: Chapter 1 Introduction
Introduction OVERVIEW The ADSP-2100 family is a collection of programmable single-chip microprocessors that share a common base architecture optimized for digital signal processing (DSP) and other high-speed numeric processing applications. The various family processors differ principally in the type of on-chip peripherals they add to the base architecture. On-chip memory, a timer, serial port(s), and parallel ports are available in different members of the family.
Page 14 16 data pins and 11 control pins. The HIP is extremely flexible and has provisions to allow simple interface to a variety of host processors. For example, the Motorola 68000, the Intel 8051, or another ADSP-2100 family processor can be easily connected to the HIP.
Page 15: Memory And System Interface
The converters use sigma-delta technology to capture data samples from a highly oversampled signal. The ADSP-2100 family architecture exhibits a high degree of parallelism, tailored to DSP requirements. In a single cycle, any device in the family can: • Generate the next program address.
Page 16: Instruction Set
Multiple programs can be selected and loaded with no additional hardware. ADSP-2100 family processors differ in their response to interrupts. In all cases, however, the program sequencer allows the processor to respond with minimum latency. Interrupts can be nested with no additional latency.
Page 17: Core Architecture
• Single-Cycle Fetch of Two Operands—In extended sums-of-products calculations, two operands are needed on each cycle to feed the calculation. All members of the ADSP-2100 family are able to sustain two-operand data throughput, whether the data is stored on-chip or off.
Page 18: Computational Units
Figure 1.1 Base Architecture 1.2.1 Computational Units Every processor in the ADSP-2100 family contains three independent, full- function computational units: an arithmetic/logic unit (ALU), a multiplier/accumulator (MAC) and a barrel shifter. The computation units process 16-bit data directly and provide hardware support for multiprecision computation as well.
Page 19: Address Generators & Program Sequencer
Introduction 1 All three units contain input and output registers which are accessible from the internal data memory data (DMD) bus. Computational operations generally take their operands from input registers and load the result into an output register. The registers act as a stopover point for data between memory and the computational circuitry.
Page 20: Buses
8-bit width discrepancy between the two buses, when necessary. ON-CHIP PERIPHERALS This section describes the additional functional units which are included in various processors of the ADSP-2100 family. 1.3.1 Serial Ports Most ADSP-21xx processors have two bidirectional, double-buffered serial ports (SPORTs) for serial communications.
Page 21: Timer
Introduction 1 serial port, SPORT1, may optionally be configured as two additional external interrupt pins ( IRQ1 and IRQ0 )and the Flag Out (FO) and Flag In (FI) pins. 1.3.2 Timer The programmable interval timer provides periodic interrupt generation. An 8-bit prescaler register allows the timer to decrement a 16-bit count register over a range from each cycle to every 256 cycles.
Page 22: Analog Interface
(DAC) and a differential output amplifier. ADSP-2100 FAMILY DEVELOPMENT TOOLS The ADSP-2100 family is supported with a complete set of software and hardware development tools. The ADSP-2100 Family Development System includes software utilities for program development and EZ Tools for hardware/software debugging.
Page 23: Organization Of This Manual
(DAGs) and the PMD-DMD bus exchange unit. Chapters 5, 6, 7, and 8 describe the additional functional units included in different members of the ADSP-2100 family. (See Table 1.1 for a list of the functions included in each device.) • Chapter 5, “Serial Ports,” describes the serial ports, SPORT0 and SPORT1.
Page 24 • Appendix B, “Division Exceptions,” describes signed and unsigned division. • Appendix C, “Numeric Formats,” describes the fixed-point numerical formats directly supported by the ADSP-2100 family, discusses block floating-point arithmetic, and tells how to handle the results of multiplication for operands of various formats.
Page 25: Chapter 2 Computational Units
Every device in the ADSP-2100 family is a 16-bit, fixed-point machine. Most operations assume a twos-complement number representation, while others assume unsigned numbers or simple binary strings. Special features support multiword arithmetic and block floating-point.
Page 26: Fractional Representation: 1.15
2 Computational Units 2.1.4 Fractional Representation: 1.15 ADSP-2100 family arithmetic is optimized for numerical values in a fractional binary format denoted by 1.15 (“one dot fifteen”). In the 1.15 format, there is one sign bit (the MSB) and fifteen fractional bits representing values from –1 up to one LSB less than +1.
Page 27: Mac Arithmetic
40-bit width of the MR register set. The ADSP-2100 family supports two modes of format adjustment: the fractional mode for fractional operands, 1.15 format (1 signed bit, 15 fractional bits), and the integer mode for integer operands, 16.0 format.
Page 28: Summary
Table 2.1 summarizes some of the arithmetic characteristics of ADSP-2100 family operations. In addition to the numeric types described in this section, the ADSP-2100 Family C Compiler supports a form of 32-bit floating-point in which one 16-bit word is the exponent and the other word is the mantissa.
Page 29: Arithmetic/Logic Unit (Alu)
Computational Units ARITHMETIC/LOGIC UNIT (ALU) The arithmetic/logic unit (ALU) provides a standard set of arithmetic and logical functions. The arithmetic functions are add, subtract, negate, increment, decrement and absolute value. These are supplemented by two division primitives with which multiple cycle division can be constructed. The logic functions are AND, OR, XOR (exclusive OR) and NOT.
Page 30 2 Computational Units The output of the ALU is loaded into either the ALU feedback (AF) register or the ALU result (AR) register. The AF register is an ALU internal register which allows the ALU result to be used directly as the ALU Y input.
Page 31: Standard Functions
Computational Units Any of the registers associated with the ALU can be both read and written in the same cycle. Registers are read at the beginning of the cycle and written at the end of the cycle. A register read, therefore, reads the value loaded at the end of a previous cycle.
Page 32: Alu Input/Output Registers
2 Computational Units 2.2.3 ALU Input/Output Registers The sources of ALU input and output registers are shown below. Source for Source for Destination for X input port Y input port R output port AX0, AX1 AY0, AY1 MR0, MR1, MR2 SR0, SR1 MR0, MR1 and MR2 are multiplier/accumulator result registers;...
Page 33: Alu Overflow Latch Mode
Computational Units When the ALU saturation mode is used, only the AR register saturates; if the AF register is the destination, wrap-around will occur but the flags will reflect the saturated result. 2.2.6 ALU Overflow Latch Mode The ALU overflow latch mode, enabled by setting bit 2 in the mode status register (MSTAT), causes the AV bit to “stick”...
Page 34 2 Computational Units LEFT SHIFT LOWER DIVIDEND UPPER DIVIDEND DIVISOR R-BUS R = PASS Y 15 LSBs Figure 2.3 DIVS Operation When dividing unsigned numbers, the DIVS operation is not used. Instead, the AQ bit in the arithmetic status register (ASTAT) should be initialized to zero by manually clearing it.
Page 35 Computational Units divisor MSB and the ALU output MSB, and the quotient bit is this value inverted. The quotient bit is loaded into the LSB of the AY0 register which is also shifted left by one bit. The DIVQ operation is illustrated in Figure 2.4. LEFT SHIFT LOWER DIVIDEND...
Page 36 (in 16.0 format), you must shift the dividend one bit to the left (into 31.1 format) before dividing. Additional discussion and code examples can be found in the handbook Digital Signal Processing Applications Using the ADSP-2100 Family, Volume 1. Dividend BBBBB.BBBBBBBBBBBBBBBBBBBBBBBBBBB...
Page 37: Alu Status
Computational Units 2.2.8 ALU Status The ALU status bits in the ASTAT register are defined below. Complete information about the ASTAT register and specific bit mnemonics and positions is provided in the Program Control chapter. Flag Name Definition Zero Logical NOR of all the bits in the ALU result register. True if ALU output equals zero.
Page 38 2 Computational Units PMD BUS 16 (UPPER) DMD BUS REGISTERS REGISTERS 2 x 16 2 x 16 REGISTER MULTIPLIER ADD / SUBTRACT REGISTER REGISTER REGISTER R - BUS Figure 2.6 MAC Block Diagram 2 – 14...
Page 39 Computational Units The input/output registers of the MAC are similar to the ALU. The X input port can accept data from either the MX register file or from any register on the result (R) bus. The R bus connects the output registers of all the computational units, permitting them to be used as input operands directly.
Page 40: Mac Operations
Multiply X and Y operands and subtract result from MR register. Clear result (MR) to zero. The ADSP-2100 family provides two modes for the standard multiply/ accumulate function: fractional mode for fractional numbers (1.15), and integer mode for integers (16.0).
Page 41 Computational Units MULTIPLIER P OUTPUT P SIGN 31 31 31 31 31 31 31 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 15 14 13 12 11 10 9 15 14 13 12 11 10 9 Figure 2.7 Fractional Multiplier Result Format P SIGN...
Page 42: Input Formats
2 Computational Units 2.3.2.2 Input Formats To facilitate multiprecision multiplications, the multiplier accepts X and Y inputs represented in any combination of signed twos-complement format and unsigned format. X input Y input signed signed unsigned signed signed unsigned unsigned unsigned The input formats are specified as part of the instruction.
Page 43: Mac Overflow And Saturation
Computational Units The 8-bit MR2 register is tied to the lower 8 bits of these buses. When MR2 is output onto the DMD bus or the R bus, it is sign extended to form a 16- bit value. MR1 also has an automatic sign-extend capability. When MR1 is loaded from the DMD bus, every bit in MR2 will be set to the sign bit (MSB) of MR1, so that MR2 appears as an extension of MR1.
Page 44: Rounding Mode
2 Computational Units 2.3.2.6 Rounding Mode The accumulator has the capability for rounding the 40-bit result R at the boundary between bit 15 and bit 16. Rounding can be specified as part of the instruction code. The rounded output is directed to either MR or MF. When rounding is invoked with MF as the output register, register contents in MF represent the rounded 16-bit result.
Page 45: Biased Rounding (Adsp-217X/218X/21Msp5X)
Computational Units Example 2 Unrounded value: xxxxxxxx xxxxxxxx01100110 1000000000000000 Bit 15 = 1 and bits 0-14 = 0 Add 1 to bit 15 and carry xxxxxxxx xxxxxxxx01100111 0000000000000000 Since bit 16 = 1, force it to 0 Rounded value: xxxxxxxx xxxxxxxx01100110 0000000000000000 In this last case, bit 16 is forced to zero.
Page 46: Barrel Shifter
2 Computational Units BARREL SHIFTER The shifter provides a complete set of shifting functions for 16-bit inputs, yielding a 32-bit output. These include arithmetic shift, logical shift and normalization. The shifter also performs derivation of exponent and derivation of common exponent for an entire block of numbers. These basic functions can be combined to efficiently implement any degree of numerical format control, including full floating-point representation.
Page 47 Computational Units DMD BUS REGISTER REGISTER EXPONENT COMPARE DETECTOR SHIFTER HI / LO ARRAY OR / PASS REGISTER NEGATE From REGISTER REGISTER INSTRUCTION R - BUS Figure 2.9 Shifter Block Diagram Any of the SI, SE or SR registers can be read and written in the same cycle. Registers are read at the beginning of the cycle and written at the end of the cycle.
Page 48 2 Computational Units The shifter contains a duplicate bank of registers, shown in Figure 2.9 behind the primary registers. There are actually two sets of SE, SB, SI, SR1, and SR0 registers. Only one bank is accessible at a time. The additional bank of registers can be activated for extremely fast context switching.
Page 49 Computational Units Control Code Shifter Array Output ABCDEFGHIJKLMNPR represents the 16-bit HI reference LO Reference input pattern +16 to +127 +32 to +127 00000000 00000000 00000000 00000000 X stands for the R0000000 00000000 00000000 00000000 PR000000 00000000 00000000 00000000 extension bit NPR00000 00000000 00000000 00000000 MNPR0000 00000000 00000000 00000000 LMNPR000 00000000 00000000 00000000...
Page 50 2 Computational Units The exponent detector derives an exponent for the shifter input value. The exponent detector operates in one of three ways which determine how the input value is interpreted. In the HI state, the input is interpreted as a single precision number or the upper half of a double precision number.
Page 51 Computational Units S = Sign bit N = Non-sign bit D = Don’t care bit HI Mode HIX Mode Shifter Array Input Output Shifter Array Input Output DDDDDDDD DDDDDDDD SNDDDDDD DDDDDDDD SNDDDDDD DDDDDDDD SSNDDDDD DDDDDDDD SSNDDDDD DDDDDDDD SSSNDDDD DDDDDDDD SSSNDDDD DDDDDDDD SSSSNDDD DDDDDDDD SSSSNDDD DDDDDDDD SSSSSNDD DDDDDDDD...
Page 52: Shifter Operations
2 Computational Units 2.4.2 Shifter Operations The shifter performs the following functions (instruction mnemonics shown in parentheses): • Arithmetic Shift (ASHIFT) • Logical Shift (LSHIFT) • Normalize (NORM) • Derive Exponent (EXP) • Block Exponent Adjust (EXPADJ) These basic shifter instructions can be used in a variety of ways, depending on the underlying arithmetic requirements.
Page 53: Derive Block Exponent
Computational Units 2.4.2.2 Derive Block Exponent This function detects the exponent of the number largest in magnitude in an array of numbers. The EXPADJ instruction performs this function. The sequence of steps for a typical example is shown below. A. Load SB with –16 The SB register is used to contain the exponent for the entire block.
Page 54: Immediate Shifts
2 Computational Units 2.4.2.3 Immediate Shifts An immediate shift simply shifts the input bit pattern to the right (downshift) or left (upshift) by a given number of bits. Immediate shift instructions use the data value in the instruction itself to control the amount and direction of the shifting operation.
Page 55: Denormalize
Computational Units In addition to the direction of the shifting operation, the shift may be either arithmetic (ASHIFT) or logical (LSHIFT). For example, the following shows a logical shift, relative to the upper half of SR (HI): SI=0xB6A3; SR=LSHIFT SI BY –5 (HI); Input: 10110110 10100011 Shift value: -5...
Page 56 2 Computational Units Two examples of denormalizing a double-precision number are given below. The first shows a denormalization in which the upper half of the number is shifted first, followed by the lower half. Since computations may produce output in either order, the second example shows the same operation in the other order, i.e.
Page 57: Normalize
Computational Units 2.4.2.5 Normalize Numbers with redundant sign bits require normalizing. Normalizing a number is the process of shifting a twos-complement number within a field so that the rightmost sign bit lines up with the MSB position of the field and recording how many places the number was shifted. The operation can be thought of as a fixed-point to floating-point conversion, generating an exponent and a mantissa.
Page 58 2 Computational Units For the first stage, the upper half of the input must be operated on first. This first exponent derivation loads the exponent value into SE. The second exponent derivation, operating on the lower half of the number will not alter the SE register unless SE = –15.
Page 59 Computational Units If the upper half of the input contains all sign bits, the SE register value is determined by the second derive exponent operation as shown below. 1. Detect Exponent, Modifier = HI First Input: (Must be upper half) 11111111 11111111 SE set to: 2.
Page 60 2 Computational Units There is one additional normalization situation, requiring the HI-extended (HIX) state. This is specifically when normalizing ALU results (AR) that may have overflowed. This operation reads the arithmetic status word (ASTAT) overflow bit (AV) and the carry bit (AC) in conjunction with the value in AR.
Page 61: Chapter 3 Program Control
Program Control OVERVIEW This chapter describes the program sequencer of the ADSP-2100 family processors. The program sequencer circuitry controls the flow of program execution. It contains an interrupt controller and status and condition logic. PROGRAM SEQUENCER The program sequencer generates a stream of instruction addresses and provides flexible control of program flow.
Page 62 Program Control DMD BUS from INSTRUCTION REGISTER COUNT CONDITION CODE STACK ADDRESS OF JUMP/CALL FUNCTION FIELD ADDRESS OF LAST INSTRUCTION IN LOOP & TERMINATION CONDITION CNTR (Counter) LOOP STATUS STACK STACK CONDITION LOOP LOGIC COMPARATOR STATUS REGISTERS ARITHMETIC STATUS (from ALU) PROGRAM COUNTER STACK...
Page 63: Next Address Select Logic
Program Control 3.2.1 Next Address Select Logic While the processor is executing an instruction, the program sequencer pre-fetches the next instruction. The sequencer’s next address select logic generates a program memory address (for the pre-fetch) from one of four sources: •...
Page 64: Program Counter & Pc Stack
Program Control 3.2.2 Program Counter & PC Stack The program counter (PC) is a 14-bit register which always contains the address of the currently executing instruction. The output of the PC is fed into a 14-bit incrementer which adds 1 to the current PC value. The output of the incrementer can be selected by the next address multiplexer to fetch the next sequential instruction.
Page 65: Loop Comparator & Stack
Program Control The counter may also be tested and automatically decremented by a conditional jump instruction that tests CE. The counter is not decremented when CE is checked as part of a conditional return or conditional arithmetic instruction. The counter may be read directly over the DMD bus at any time without affecting its contents.
Page 66 Program Control The loop stack stores the last instruction addresses and termination conditions of temporarily dormant loops. Up to four levels can be stored. The only extra cycle associated with the nesting of DO UNTIL loops is the execution of the DO UNTIL instruction itself, since the pushing and popping of all stacks associated with the looping hardware is automatic.
Page 67 Program Control At this point, there are three possible results depending on the type of instruction at the end of the loop. Case 1 illustrates the most typical situation. Cases 2 and 3 are also allowed but involve greater program complexity for proper execution.
Page 68: Program Control Instructions
Program Control Note: Caution is required when ending a loop with a JUMP, CALL, RETURN, or IDLE instruction, or when making a premature exit from a loop. Since none of the loop sequencing mechanisms are active while the jump/call/return is being performed, the loop, PC, and counter stacks are left with the looping information (since they are not popped).
Page 69: Call Instruction
Program Control 3.3.2 CALL Instruction The CALL instruction executes in a similar fashion as the JUMP instruction. The address of the subroutine is embedded in the CALL instruction word and, once extracted from the instruction register, is fed back the PC for the next cycle. In addition, the current value of the program counter is incremented and pushed onto the PC stack.
Page 70: Idle Instruction
Program Control Execution of the DO UNTIL instruction pushes the address of the instruction immediately following the DO UNTIL onto the PC stack (by pushing the incremented PC). On the same cycle, the loop stack is pushed with the address of the end-of-loop instruction and the termination condition.
Page 71: Interrupts
Tables 3.2–3.7 show the interrupts and associated vector addresses for each processor of the ADSP-2100 family. (Note that SPORT1 can be configured as either a serial port or as a collection of control pins including two external interrupt inputs, IRQ0 and IRQ1 .
Page 72 The ADSP-2100 family processors include a secondary register set which can be used to provide a fresh set of ALU, MAC, and Shifter registers during interrupt servicing.
Page 73 Program Control Interrupt Source Interrupt Vector Address RESET startup (or powerup w/PUCR=1) 0x0000 (highest priority) Powerdown (non-maskable) 0x002C IRQ2 0x0004 HIP Write (from Host) 0x0008 HIP Read (to Host) 0x000C SPORT0 Transmit 0x0010 SPORT0 Receive 0x0014 Software Interrupt 1 0x0018 Software Interrupt 2 0x001C SPORT1 Transmit or IRQ1...
Page 74: Interrupt Servicing Sequence
Program Control 3.4.1 Interrupt Servicing Sequence When an interrupt request occurs, it is latched while the processor finishes executing the current instruction. The interrupt request is then compared with the interrupt mask register, IMASK, by the interrupt controller. If the interrupt is not masked, the program sequencer pushes the current value of the program counter (which contains the address of the next instruction) onto the PC stack—this allows execution to continue, after the interrupt is serviced, with the next instruction of the main program.
Page 75: Interrupt Control Register (Icntl)
Program Control Edge-sensitive interrupt inputs generally require less external hardware than level-sensitive inputs, and allow signals such as sampling-rate clocks to be used as interrupts. A level-sensitive interrupt must remain asserted until the interrupt is serviced. The interrupting device must then deassert the interrupt request so that the interrupt is not serviced again.
Page 76: Interrupt Mask Register (Imask)
Program Control 3.4.2.2 Interrupt Mask Register (IMASK) Each bit of the IMASK register enables or disables the servicing of an individual interrupt. Specific bit definitions for each processor’s IMASK register are given in Appendix E, “Control/Status Registers.” The mask bits are positive sense: 0=masked, 1=enabled. IMASK is set to zero upon a processor reset.
Page 77: Global Enable/Disable For Interrupts
Program Control ICNTL Interrupt Nesting Enable bit = 0 (nesting disabled) Interrupt IMASK contents before IMASK contents entering level serviced (pushed on stack) interrupt service routine 0 (low) ijklmn 000000 ijklmn 000000 ijklmn 000000 ijklmn 000000 ijklmn 000000 5 (high) ijklmn 000000 ICNTL Interrupt Nesting Enable bit = 1 (nesting enabled)
Page 78: Interrupt Force & Clear Register (Ifc)
Program Control 3.4.2.4 Interrupt Force & Clear Register (IFC) IFC is a write-only register that allows the forcing and clearing of edge- sensitive interrupts in software. An interrupt is forced or cleared under program control by setting the force or clear bit corresponding to the desired interrupt.
Page 79 Program Control CLKOUT Interrupt Instruction 1st instr of n–2 n–1 Executing serv routine Address for interrupt n–1 Instruction Fetch vector i Figure 3.2 Interrupt Latency (Timer, , SPORT, HIP, & Analog Interrupts) IRQx x x x x (Note that this latency for the timer interrupt only applies for the ADSP-2171, ADSP-2181, and ADSP-21msp58/59 processors.
Page 80: Status Registers & Status Stack
Program Control STATUS REGISTERS & STATUS STACK Processor status and mode bits are maintained in internal registers which can be independently read and written over the DMD bus. These registers are: ASTAT Arithmetic status register SSTAT Stack status register(read-only) MSTAT Mode status register ICNTL Interrupt control register IMASK...
Page 81: Stack Status Register (Sstat)
Program Control Each of the bits is automatically updated when a new status is generated by an arithmetic instruction. Each bit is affected only by a subset of arithmetic operations, as defined by the following table: Status Bit Updated by AZ, AN, AV, AC Any ALU operation except DIVS, DIVQ ALU absolute value operation (ABS)
Page 82: Mode Status Register (Mstat)
Program Control The empty status bits indicate that the number of pop operations for the stack is greater than or equal to the number of push operations that have occurred since the last processor reset. The overflow status bits indicate that the number of push operations for the stack has exceeded the number of pop operations, by an amount that is greater than the total depth of the stack.
Page 83 1 (DAG1). This is useful for reordering the input or output data of an FFT algorithm. The ADSP-2100 family processors include a secondary register set which can be used to provide a fresh set of ALU, MAC, and Shifter registers at any time, for example during execution of a subroutine.
Page 84: Conditional Instructions
Program Control The ALU overflow latch mode causes the AV status bit to “stick” once it is set. In this mode, AV will be set by an overflow and will remain set even if subsequent ALU operations do not generate overflows. AV can then be cleared only by writing a zero into it.
Page 85: Toppcstack
Program Control Syntax Status Condition True If: Equal Zero AZ = 1 Not Equal Zero AZ = 0 Less Than Zero AN .XOR. AV = 1 Greater Than or Equal Zero AN .XOR. AV = 0 Less Than or Equal Zero (AN .XOR.
Page 86 Program Control There is no standard PUSH PC stack instruction. To push a specific value onto the PC stack, therefore, use the following special instruction: TOPPCSTACK = reg; {push reg contents onto PC stack} The stack is pushed immediately, in the same cycle. Examples: AX0 = TOPPCSTACK;...
Page 87: Toppcstack Restrictions
Program Control 3.7.1 TOPPCSTACK Restrictions There are several restrictions on the use of the special TOPPCSTACK instructions, as described below. 1.) The pop and read TOPPCSTACK instruction may not be placed directly before an RTI instruction (return from interrupt). A NOP must be inserted in between: reg = TOPPCSTACK;...
Page 88 Program Control 3 instruction 3; {if this is an RTS, RTI, or POP PC … } then the following restrictions must be observed: - instruction 2 may not be either the pop/read or push/write TOPPCSTACK instruction. - If instruction 3 is also the last instruction of a Do Until loop, then instruction 1 may not be the push/write TOPPCSTACK instruction.
Page 89: Chapter 4 Data Transfer
PMD-DMD bus exchange unit. DATA ADDRESS GENERATORS (DAGS) Every device in the ADSP-2100 family contains two independent data address generators so that both program and data memories can be accessed simultaneously. The DAGs provide indirect addressing capabilities.
Page 90 4 Data Transfer DMD BUS FROM INSTRUCTION FROM INSTRUCTION MODULUS REGISTERS REGISTERS REGISTERS LOGIC 4 x 14 4 x 14 4 x 14 DAG1 ONLY REVERSE ADDRESS Figure 4.1 Data Address Generator Block Diagram The I registers (I0-I3 in DAG1, I4-I7 in DAG2) contain the actual addresses used to access memory.
Page 91: Indirect Addressing
4.2.2 Indirect Addressing The ADSP-2100 family processors allow two addressing modes for data memory fetches: direct and register indirect. Indirect addressing is accomplished by loading an address into an I (index) register and specifying one of the available M (modify) registers.
Page 92: Modulo Addressing (Circular Buffers)
4 Data Transfer Here is a simple example of linear indirect addressing: I3=0x3800; M2=0; L3=0; AX0=DM(I3,M2); Here is an example which uses a memory variable to store an address pointer: .VAR/DM/RAM addr_ptr; {variable holds address to be accessed} I3=DM(addr_ptr); {I3 loaded using direct addressing} L3=0;...
Page 93: Calculating The Base Address
Data Transfer 4.2.4 Calculating The Base Address The base address of a circular buffer of length L is 2 or a multiple of 2 where n satisfies the condition: < L ≤ 2 In other words, the base address is L “rounded” upwards to the closest power of 2 (or its multiple).
Page 94: Circular Buffer Operation Example 2
N is the number of bits you wish to output reversed. For a complete example of this, refer to Section 6.6.5.2 “Modified Butterfly” in Chapter 6, One-Dimensional FFTs, of the applications handbook Digital Signal Processing Applications Using the ADSP-2100 Family (Volume 1). 4 – 6...
Page 95: Programmng Data Accesses
Data Transfer PROGRAMMING DATA ACCESSES The ADSP-2100 Family Development Software supports the declaration and use of a simple data structure: one-dimensional arrays, or buffers. The array may contain a single value (a variable) or multiple values (an array). In addition, the array may be used as a circular buffer. Here is a brief discussion of each instance, with an example of how they are declared and used in assembly language.
Page 96: Circular Buffers
4 Data Transfer It is also possible to initialize a complete array/buffer from a data file, using the .INIT directive: .INIT coefficients: <filename.dat>; This assembler directive reads the values from the file filename.dat into the array at link time. This feature is supported only in the simulator — data cannot be loaded directly into on-chip data memory by the hardware booting sequence.
Page 97: Pmd-Dmd Bus Exchange
Data Transfer PMD-DMD BUS EXCHANGE The PMD-DMD bus exchange unit couples the program memory data bus and the data memory data bus, allowing them to transfer data between them in both directions. Since the program memory data (PMD) bus is 24 bits wide, while the data memory data (DMD) bus is 16 bits wide, only the upper 16 bits of PMD can be directly transferred.
Page 98 4 Data Transfer The first type of connection is a one-way path from each bus to the other. This is implemented with two tristate buffers connecting the DMD bus with the upper 16 bits of the PMD bus. One of these two buffers is normally used when data is exchanged between the program memory and one of the registers connected to the DMD bus.
Page 99 Data Transfer stored to the 8 lower bits of the memory word. From the DMD bus, the PX register may be: 1. Loaded with a data move instruction, explicitly specifying the PX register as the destination. The lower 8 bits of the data value are used and the upper 8 are discarded.
Page 100: Overview
Serial Ports OVERVIEW Synchronous serial ports, or SPORTs, support a variety of serial data communications protocols and can provide a direct interconnection between processors in a multiprocessor system. These ADSP-2100 family processors contain serial ports: Number of Processor Serial Ports ADSP-2101...
Page 101 5 Serial Ports A SPORT receives serial data on its DR input and transmits serial data on its DT output. It can receive and transmit simultaneously, for full duplex operation. The data bits are synchronous to the serial clock SCLK, which is an output if the processor generates this clock or an input if the clock is generated externally.
Page 102 Serial Ports • Bidirectional: each SPORT has independent transmit and receive sections. • Double-buffered: each SPORT section (both receive and transmit) has a data register for transferring data words to and from other parts of the processor and a register for shifting data in or out. The double- buffering provides additional time to service the SPORT.
Page 103: Interrupts
5 Serial Ports interrupt inputs, IRQ0 and IRQ1, and the Flag In and Flag Out signals instead of as a serial port. The internally generated serial clock may still be used in this configuration. See Section 5.4. 5.2.1 Interrupts Each SPORT has a receive interrupt and a transmit interrupt. The priority of these interrupts is shown in Table 5.2.
Page 104: Sport Configuration
Serial Ports The configuration section is a block of control registers (mapped to data memory) that the program must initialize before using the SPORTs. The data section is a register file used to transmit and receive values through the SPORT. 5.3.1 SPORT Configuration SPORT configuration is accomplished by setting bit and field values in...
Page 105: Receiving And Transmitting Data
5 Serial Ports configuration registers: write a register to an immediate address (instruction type 3) or write immediate data to an indirect address (instruction type 2). With either method, it is important to configure the serial port before enabling it. The first method of programming configuration registers requires no setup of DAG registers but does require two instructions to perform the write.
Page 106: Sport Enable
Serial Ports load of a non-data register with immediate data or register-to-register move (instruction types 3, 7 and 17). For example, the following instruction would ready SPORT1 to transmit a serial value, assuming SPORT1 is configured and enabled: TX1 = AX0; {the contents of AX0 are transmitted} {on SPORT1} The following instruction would access a serial value received on SPORT0:...
Page 107: Serial Clocks
5 Serial Ports are cleared at reset, disabling both SPORTs. Bit 10 of the system control register determines the configuration of SPORT1, either as a serial port or as interrupts and flags, according to Table 5.4 on the next page. If bit 10 is a 1, SPORT1 operates as a serial port; if it is a 0, the alternate functions are in effect (and bit 11 is ignored).
Page 108: Word Length
Serial Ports External serial clock frequencies may be as high as the processor’s cycle rate, up to a maximum of 13.824 MHz; internal clock frequencies may be as high as one-half the processor’s clock rate. The frequency of an internally generated clock is a function of the processor clock frequency (as seen at the CLKOUT pin) and the value of the 16-bit serial clock divide modulus register SCLKDIV (0x3FF5 for SPORT0 and 0x3FF1 for SPORT1).
Page 109: Word Framing Options
5 Serial Ports SPORT0 Control Register: 0x3FF6 SPORT1 Control Register: 0x3FF2 SLEN (Serial Word Length – 1) Figure 5.4 SLEN Field In SPORT Control Register For example, if you are using 8-bit serial words, set SLEN to 7 (0111 binary). The SLEN field is bits 3-0 in the SPORT control register (0x3FF6 for SPORT0 and 0x3FF2 for SPORT1).
Page 110: Frame Synchronization
Serial Ports 5.7.1 Frame Synchronization Word framing signals are optional. If the receive frame sync required (RFSR) or transmit frame sync required (TFSR) bit in the SPORT control register is a 0, a frame sync signal is necessary to initiate communications but is ignored after the first bit is transferred.
Page 111 5 Serial Ports on its frame sync pin (RFS or TFS). If the IRFS or ITFS bit is a 1, the processor generates its own frame sync signal and drives the RFS or TFS pin as an output. The IRFS bit is bit 8 in the SPORT control register (0x3FF6 for SPORT0 and 0x3FF2 for SPORT1), and the ITFS bit is bit 9.
Page 112: Normal And Alternate Framing Modes
Serial Ports SCLK is supplied externally. This provides a way to divide external clocks for any purpose. You can also use one frame sync to generate a single signal for both transmit and receive data. For example, an internally generated RFS (output) could be connected to an externally generated TFS (input) on the same SPORT for simultaneous transmit and receive operations.
Page 113: Active High Or Active Low
5 Serial Ports Framing modes for receiving and transmitting data are independent. If the receive frame sync width (RFSW) bit or transmit frame sync width (TFSW) bit in the SPORT control register is a 0, normal framing is enabled. If the RFSW or TFSW bit is a 1, alternate framing is used.
Page 114: Configuration Example
Serial Ports regardless of the source of frame sync signals; they either control the polarity of internally generated signals or determine how externally generated signals are interpreted. The INVRFS bit is bit 6 in the SPORT control register (0x3FF6 for SPORT0 and 0x3FF2 for SPORT1), and the INVTFS bit is bit 7.
Page 115 5 Serial Ports (continued from previous page) {SPORT0 inits} {Assumes a CLKIN of 12.288 MHz. Internally generated} {SCLK will be 2.048 MHz, and framing sync of 8 kHz} AX0 = 255; DM(0x3FF4) = AX0; {RFSDIV = 256, 256 SCLKs between} {frame syncs: 8 kHz framing} AX0 = 2;...
Page 116 Serial Ports SCLK OUTPUT INPUT SPORT Control Register: Internal Frame Sync 0X10 XXX1 X0XX 0011 External Frame Sync 0X10 XXX0 X0XX 0011 Both Internal Framing Option and External Framing Option Shown Figure 5.10 SPORT Receive, Normal Framing SCLK OUTPUT INPUT SPORT Control Register: Internal Frame Sync 0X10 XXX1 X0XX 0011...
Page 117 5 Serial Ports SCLK OUTPUT INPUT SPORT Control Register: Internal Frame Sync 0X11 XXX1 X0XX 0011 External Frame Sync 0X11 XXX0 X0XX 0011 Both Internal Framing Option and External Framing Option Shown Figure 5.12 SPORT Receive, Alternate Framing SCLK OUTPUT INPUT SPORT Control Register: Internal Frame Sync...
Page 118 Serial Ports = low, and X can be either. The underlined bit values are the bits which set the modes illustrated in the example. Figures 5.10 to 5.15 show framing for receiving data. In Figures 5.10 and 5.11, the normal framing mode is shown for noncontinuous data (any number of SCLK cycles between words) and continuous data (no SCLK cycles between words).
Page 119 5 Serial Ports continuous receiving in the alternate framing mode. In these four figures, both the input timing requirement for an externally generated frame sync and the output timing characteristic of an internally generated frame sync are shown. Note that the output meets the input timing requirement; thus, on processors with two SPORTs, one SPORT could provide RFS for the other.
Page 120 Serial Ports SCLK OUTPUT INPUT SPORT Control Register: Internal Frame Sync 0XXX 111X 0XXX 0011 External Frame Sync 0XXX 110X 0XXX 0011 Both Internal Framing Option and External Framing Option Shown Note: There is an asynchronous delay between TFS input and DT. See the appropriate data sheet for specifications.
Page 121 5 Serial Ports Figures 5.14 and 5.15 show the receive operation with normal framing and alternate framing, respectively, in the unframed mode. There is a single the frame sync signal that occurs only at the start of the first word, either one SCLK before the first bit (normal) or at the same time as the first bit (alternate).
Page 122: Companding And Data Format
Serial Ports Figures 5.16 to 5.21 show framing for transmitting data and are very similar to Figures 5.10 to 5.15. In Figures 5.16 and 5.17, the normal framing mode is shown for noncontinuous data and continuous data. Figures 5.18 and 5.19 show noncontinuous and continuous transmission in the alternate framing mode.
Page 123: Companding Operation Example
5 Serial Ports The ADSP-2100 family of processors supports both of the widely used algorithms for companding: A-law and µ-law. The processor compands data according to the CCITT G.711 recommendation. The type of companding can be selected independently for each SPORT.
Page 124: Contention For Companding Hardware
Serial Ports generates the transmit interrupt to indicate that TXn is ready for the next data word. If the framing signal is being provided externally, the next word must be written to TXn early enough to allow for compression before the next framing signal arrives. Here is a typical sequence of operations for receiving companded data: •...
Page 125: Autobuffering
5 Serial Ports The code might look like this: TX0 = AX0; {linear data written to transmit register} NOP; {any instruction} AX1 = TX0; {compressed data transferred to AX1} Use the same procedure to expand data, but use RXn instead of TXn. RX0 = AX0;...
Page 126 Serial Ports the overhead cycle. A delay in the autobuffer transfer occurs if the transfer is required during an instruction executing in multiple cycles (for wait states, for example). If the transfer is required when the processor is waiting in an IDLE state, the transfer is executed and the processor returns to IDLE.
Page 127: Autobuffering Control Register
5 Serial Ports In the worst case that all four autobuffer transfers are required at about the same time, interrupt latency would increase by the time it takes for all the transfers to occur, which is affected by wait states and bus request. 5.11.1 Autobuffering Control Register In autobuffering mode, an interrupt is generated when the modification of a specified I register (in the DAG) by the value in the specified M register...
Page 128 Serial Ports last value has been loaded into the transmit shift register. A receive interrupt will be generated once the rx_buffer has been completely filled. .MODULE/RAM code_to_init_AB_SPORT1; {—— Initialization code for autobuffer ——} .VAR/DM/CIRC tx_buffer[10]; .VAR/DM/CIRC rx_buffer[10]; .ENTRY sport1_inits; {set up I,M, and L registers} sport1_inits: I0 = ^tx_buffer;...
Page 129: Multichannel Function
5 Serial Ports IMASK = 6; {enable SPORT1 interrupts} {enable SPORT1} AX0 = 0x0C1F; {enable SPORT1 leave PWAIT,} DM(0x3FFF) = AX0; {BWAIT as default} {Place first transfer value into TX1} AX0 = DM(I0,M0); TX1 = AX0; RTS; .ENDMOD; Figure 5.24 Autobuffering Example Configuration Code 5.12 MULTICHANNEL FUNCTION SPORT0 supports a multichannel function.
Page 130: Multichannel Setup
Serial Ports a single word or continuous stream, with independent receive and transmit operation. In the multichannel mode, the receive frame sync signal (RFS0) identifies the start of a 24- or 32-word block of serial data with the receiver and transmitter operating in parallel. TFS0 has an alternate function, described below.
Page 131: Multichannel Operation
5 Serial Ports 0x3FFA Receive Word Enables 0x3FF9 1 = Channel Enabled 0 = Channel Ignored 0x3FF8 Transmit Word Enables 0x3FF7 word length is still set by the SLEN field in the SPORT control register and can be 3 to 16 bits. The multichannel frame delay (MFD) is a 4-bit field specifying (in binary) the number of serial clock cycles between the frame sync signal and the first data bit.
Page 132 Serial Ports WORD 0 WORD 1 WORD 2 SCLK IGNORED frame signal inversion (INVRFS), companding (DTYPE) and autobuffering are unchanged in the multichannel mode. Note: It is important that RFS does not occur more than once per frame in multichannel mode. Instead of providing frame synchronization, the TFS0 signal functions as a transmit data valid (TDV) signal in multichannel mode.
Page 133: Sport Timing Considerations
5 Serial Ports Figure 5.29 Complete Multichannel Example 5.13 SPORT TIMING CONSIDERATIONS The SPORTs support full duplex operation and are normally interrupt driven. That is, whenever a SPORT transaction has completed, the processor generates an internal interrupt. Under most operating conditions, the actual timing of the SPORT interrupts is not critical.
Page 134: Internally Generated Frame Sync Timing
Serial Ports SCLK cycle, the serial port becomes active, looking for a frame sync. 5.13.3 Internally Generarated Frame Sync Timing When internally generated frame syncs are used, all that is necessary to transmit data, from the programmer’s point of view, is to move the data into the appropriate TX register with an instruction such as: TX0 = AX0;...
Page 135: Transmit Interrupt Timing
5 Serial Ports when the data value was loaded into the transmit register. (Note that if the transmit frame sync is generated externally, data starts transmitting when a frame sync signal is received.) After the TX register is loaded, it takes three complete phases of the serial clock, HIGH, LOW and HIGH, in that order, to ensure synchronization (see Figure 5.30).
Page 136: Receive Interrupt Timing
Serial Ports BIT3 BIT2 BIT1 BIT0 SCLK Interrupt or Autobuffer Request Figure 5.32 SPORT Interrupt or Autobuffer Timing, Receive 4-Bit Words (No Companding) The transmit interrupt essentially means that it is all right to write a value to the TX register. 5.13.5 Receive Interrupt Timing The receiver portion of the SPORT latches data on the DR pin on the falling edges of SCLK.
Page 137: Interrupt And Autobuffer Synchronization
5 Serial Ports received. The interrupt request occurs on the rising edge of SCLK after a word is received (see Figure 5.32) and indicates that new data in the RX register can be read. Companding causes a delay in the same manner as for transmitting. However, the latency is transparent, as the receive interrupt is generated after the expansion has taken place.
Page 138: Instruction Completion Latencies
Serial Ports latencies exist for all external interrupts. The processor can only service interrupt or autobuffer requests on instruction cycle boundaries, so there may be additional latency cycles added due to the completion of an instruction. 5.13.7 Instruction Completion Latencies There are several situations which can cause an instruction to take more than one processor cycle.
Page 139: Interrupt And Autobuffer Service Example
5 Serial Ports • SPORT0 transmit autobuffer—highest priority (not on ADSP-2105) • SPORT0 receive autobuffer (not on ADSP-2105) • SPORT1 transmit autobuffer • SPORT1 receive autobuffer • Unmasked pending interrupts in priority order 5.13.8 Interrupt & Autobuffer Service Example Figure 5.35 shows the execution of a serial port interrupt based on a request that meets the setup and hold time requirements.
Page 140: Receive Companding Latency
Serial Ports Autobuffering only consumes the cycles necessary to perform the data transfer; no additional cycles are lost fetching instructions. The above diagram assumes that all instructions and data transfers occur in one Request SPORT0 Receive Request SPORT1 Receive CLKOUT AUTOBUFFER AUTOBUFFER EXEC...
Page 141: Interrupts With Autobuffering Enabled
This can only occur on instruction cycle boundaries and only one receive register can be expanded at a time. On the ADSP-2100 family processors that have two serial ports (i.e. all except the ADSP-2105), there is also a possibility of a delay due to the availability of the companding circuitry.
Page 142 Serial Ports If the processor is free to handle the autobuffer requests in the order they are generated, the receive autobuffer happens first and is then followed by the transmit autobuffer. The order of these operations may change if the processor is not available to handle the requests due to any of the previously mentioned latencies.
Page 143: Chapter 6 Timer
Timer OVERVIEW The programmable interval timer can generate periodic interrupts based on multiples of the processor’s cycle time. When enabled, a 16-bit count register is decremented every n cycles, where n–1 is a scaling value stored in an 8-bit register. When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register.
Page 144 6 Timer TPERIOD Period Register 0x3FFD TCOUNT Counter Register 0x3FFC TSCALE Scaling Register 0x3FFB Figure 6.1 Timer Registers TSCALE stores a scaling value that is one less than the number of cycles between decrements of TCOUNT. For example, if the value in TSCALE register is 0, the counter register decrements once every cycle.
Page 145: Resolution
Timer RESOLUTION TSCALE provides the capability to program longer time intervals between interrupts, extending the range of the 16-bit TCOUNT register. Table 6.1 shows the range and the relationship between period length and resolution for TPERIOD = maximum. Cycle Time = 80 ns TSCALE Interrupt Every…...
Page 146 6 Timer One interrupt occurs every (TPERIOD +1) * (TSCALE +1) cycles. To set the first interrupt at a different time interval from subsequent interrupts, load TCOUNT with a different value from TPERIOD. The formula for the first interrupt is (TCOUNT+1) * (TSCALE+1). If you write a new value to TSCALE or TCOUNT, the change is effective immediately.
Page 147: Chapter 7 Host Interface Port
Host Interface Port OVERVIEW The host interface port (HIP) of the ADSP-2111, ADSP-2171, and ADSP-21msp58/59 is a parallel I/O port that allows these processors to be used as memory-mapped peripherals of a host computer (i.e. slave DSP processors). Examples of host computers include the Intel 8051, Motorola 68000 family, and even other ADSP-21xx processors.
Page 148 7 Host Interface Port HIP PIN SUMMARY The HIP consists of 27 pins. As shown in Table 7.1, 16 of these are data pins and 11 are control pins. Some of the control pins have dual functions, allowing the processor to support different bus protocols. Number Name of Pins...
Page 149 Host Interface Port HSEL is a host select which allows the host to enable or disable the HIP for host data transfers. HACK is a host acknowledge output for hosts that require an acknowledge for handshaking. HSIZE configures the bus size; the HIP can function in both 8-bit and 16- bit modes.
Page 150: Hip Functional Description
7 Host Interface Port The functions of the following pins are determined by HMD0 and HMD1 as described above: HD15-0/HAD15-0 are either a data bus or a multiplexed address/data bus. (Only the 3 least significant address bits are used.) HRD/HRW is either a read strobe or a read/write select (1=read, 0=write). HWR/HDS is either a write strobe or a data strobe.
Page 151 Host Interface Port HSIZE BMODE HMD1 HMD0 HACK Host HSEL Control HWR/HDS Interface Boot HRD/HRW Control HA2/ALE HA1-0 Overwrite Bit Read/write control HDR0 HDR1 HDR2 HDR3 HDR4 HDR5 HMASK HSR6 SOFT RESET HSR7 INTERRUPTS HD15-0 Figure 7.1 HIP Block Diagram The HSR registers are shown in Figure 7.2, which can be found on the following page.
Page 152: Hip Operation
7 Host Interface Port HSR7 0x3FE7 21xx HDR0 Write 21xx HDR1 Write 21xx HDR2 Write OVERWRITE 21xx HDR3 Write MODE 21xx HDR4 Write SOFTWARE 21xx HDR5 Write RESET HSR6 0x3FE6 Host HDR0 Write Host HDR1 Write 21xx HDR5 Write Host HDR2 Write 21xx HDR4 Write Host HDR3 Write 21xx HDR3 Write...
Page 153: Polled Operation
Host Interface Port Because the HIP typically communicates with a host computer that has both a slower instruction rate and a multicycle bus cycle, the host computer is usually the limiting factor in the speed of HIP transfers. During a transfer, the ADSP-21xx executes instructions normally, independent of HIP operation.
Page 154: Hip Status Synchronization
7 Host Interface Port For example, the ADSP-21xx can wait in a loop reading an HSR bit to see if the host has written new data. When the ADSP-21xx sees that the bit is set, it conditionally jumps out of the loop, processes the new data, then returns to the loop.
Page 155: Interrupt-Driven Operation
Host Interface Port two consecutive reads—the second read will generate the correct status information (the first read generates the previous status). In Figure 7.3, host status synchronization is based on a pseudo-clock HCLK, internal to the ADSP-21xx, which is a logical combination of HRD, HWR and HSEL. The first event shown in the figure is a status change at d1.
Page 156: Software Reset
7 Host Interface Port If the HDR overwrite bit is set, the previous value in the HDR is overwritten and HACK is returned immediately. If the ADSP-21xx is reading the register that is being overwritten, the result is unpredictable. After reset, the HDR overwrite bit is set. If the host does not require an acknowledge (HACK is not used), the HDR overwrite bit should be always be set, because there is no way for the ADSP-21xx to prevent overwrite.
Page 157 Host Interface Port HMASK 0x3FE8 Host HDR0 Write Host HDR1 Write Host HDR5 Read Host HDR2 Write Host HDR4 Read Host HDR3 Write Host HDR3 Read Host HDR4 Write Host HDR2 Read Host HDR5 Write Host HDR1 Read Host HDR0 Read INTERRUPT ENABLES 1=enable 0=disable...
Page 158: Host Interface Timing
7 Host Interface Port HOST INTERFACE TIMING The following diagrams show the timings of HIP signals in the various modes determined by HMD0 and HMD1. HMD0 configures the bus strobes, selecting either separate read and write strobes or a single read/ write select and a host data strobe.
Page 159 Host Interface Port HMD0 selects separate read and write strobes, and HMD1 selects separate address and data buses. The timing for the read cycle and the write cycle is as follows: The host asserts the address. The host asserts (HRD or HWR) and HSEL. The ADSP-21xx returns HACK (and, for a read cycle, the data).
Page 160 7 Host Interface Port selects a multiplexed read/write select with data strobe, and HMD1 selects separate address and data buses. The timing for the read cycle and the write cycle is as follows: The host asserts HRW and the address. The host asserts HDS and HSEL.
Page 161 Host Interface Port for the read cycle and the write cycle is as follows: The host asserts ALE. The host drives the address. The host deasserts ALE. The host stops driving the address. The host asserts (HRD or HWR) and HSEL. The ADSP-21xx returns HACK (and, for a read cycle, the data).
Page 162: Boot Loading Through The Hip
BMODE=1, booting occurs through the HIP. To generate a file for HIP booting, use the HIP Splitter utility program of the ADSP-2100 Family Development Software. (This utility produces HIP boot files while the PROM Splitter utility produces files for EPROM booting.)
Page 163 Host Interface Port 2. The host waits at least two ADSP-21xx processor cycles. 3. Starting with the instruction which is to be loaded into the highest address of internal program memory, the host writes an instruction into HDR0, HDR2 and HDR1 (in that order), one byte each. The upper byte goes into HDR0, the lower byte goes into HDR2 and the middle byte goes into HDR1.
Page 164 7 Host Interface Port The following example shows the data that a host would write to the HIP for a 1000-instruction boot: Data Location Page Length (124 decimal) HDR3 Upper Byte of Instruction at 999 HDR0 Lower Byte of Instruction at 999 HDR2 Middle Byte of Instruction at 999 HDR1...
Page 165: Chapter 8 Analog Interface
Analog Interface OVERVIEW The ADSP-21msp58 and ADSP-21msp59 processors include an analog signal interface consisting of a 16-bit sigma-delta A/D converter, a 16- bit sigma-delta D/A converter, and a set of memory-mapped control and data registers. The analog interface offers the following features: •...
Page 166: A/D Conversion
8 Analog Interface Two ADSP-21msp58/59 interrupts are dedicated to the ADC and DAC converters. One interrupt is used for the ADC and the other interrupt is used for the DAC. Interrupts occur at the sample rate or when the autobuffer transfer is complete. A block diagram of the analog interface is shown in Figure 8.1, and pin definitions are given in Table 8.1.
Page 167: Adc
Analog Interface Pin Name Function Input terminal of the NORM channel of the ADC. NORM Input terminal of the AUX channel of the ADC. Decouple Ground reference of the NORM and AUX channels for the ADC. VOUT Non-inverting output terminal of the differential output amplifier from the DAC.
Page 168: Decimation Filter
8 Analog Interface 8.2.2.1 Decimation Filter The ADC’s anti-aliasing decimation filter contains two stages. The first stage is a sinc digital filter that increases resolution to 16 bits and reduces the sample rate to 40 kHz. The second stage is an IIR low pass filter.
Page 169: High Pass Filter
Analog Interface 8.2.2.2 High Pass Filter The ADC’s digital high pass filter removes frequency components at the low end of the spectrum; it attenuates signal energy below the passband of the converter. The ADC’s high pass filter can be bypassed by setting bit 7 (ADBY) of the ADSP-21msp58/59’s analog control register.
Page 170: D/A Conversion
8 Analog Interface D/A CONVERSION The D/A conversion circuitry of the ADSP-21msp58/59’s analog interface consists of a sigma-delta digital-to-analog converter (DAC), an analog smoothing filter, a programmable gain amplifier, and a differential output amplifier. 8.3.1 The analog interface’s DAC implements digital filters and a sigma- delta modulator with the same characteristics as the filters and modulator of the ADC.
Page 171: Interpolation Filter
Analog Interface The high pass filter is a 4th-order elliptic filter with a passband cutoff at 150 Hz. Stopband attenuation is 25 dB. This filter has the following specifications: Filter type: 4th-order high pass elliptic IIR Sample frequency: 8.0 kHz Passband cutoff: 150.0 Hz ±0.2 dB...
Page 172: Analog Smoothing Filter & Programmable Gain Amp
8 Analog Interface Figure 8.2 shows the frequency response of the IIR low pass filter. Passband ripple is ±0.2 dB for the combined effects of the DAC’s digital filters (i.e. high pass filter and IIR low pass of the interpolation filter) in the 300–3400 Hz passband.
Page 173: Operating The Analog Interface
Analog Interface OPERATING THE ANALOG INTERFACE The analog interface of the ADSP-21msp58/59 is operated with the use of several memory-mapped control and data registers. The ADC and DAC I/O data can be received and transmitted in two memory- mapped data registers. The data can also be autobuffered into (and from) on-chip memory where data is automatically transferred to or from the data registers.
Page 174: Analog Autobuffer/Powerdown Register
8 Analog Interface Analog Control Register DM(0x3FEE) DM[0x3FEE] ADC Offset ADC Input Gain (ADC PGA) ADC Input Gain (ADC PGA) ADC Input Multiplexer Select 1=AUX input, 0=NORM input DABY DAC High Pass Filter Bypass 1=bypass, 0=insert OG2, OG1, OG0 DAC Output Gain (DAC PGA) ADBY ADC High Pass Filter Bypass 1=bypass, 0=insert...
Page 175: Memory-Mapped Data Registers
Analog Interface Analog Autobuffer/Powerdown Control Register DM[0x3FEF] DM(0x3FEF) ARBUF ADC Receive Autobuffer Enable ATBUF DAC Transmit Autobuffer Enable ARMREG Processor powerdown control bits. Receive M register (See Chapter 9, “System Interface”) ARIREG Receive I register ATMREG Transmit M register ATIREG Transmit I register Figure 8.5 Analog Autobuffer/Powerdown Control Register Bits 12–15 of the analog autobuffer/powerdown register control the...
Page 176: Adc & Dac Interrupts
8 Analog Interface 8.4.3 ADC & DAC Interrupts The analog interface generates two interrupts that signal either: 1) that a 16-bit, 8 kHz analog-to-digital or digital-to-analog conversion has been completed, or 2) that an autobuffer block transfer has been completed (i.e. the entire data buffer contents have been transmitted or received).
Page 177: Autobuffering Enabled
Analog Interface { ADSP-21msp58/59 Analog Interface Loopback Example - configures analog interface - copies ADC receive data to DAC transmit buffer} .MODULE/ABS=0/BOOT=0 talkthru; #define codec_tx_data 0x3FEC #define codec_rx_data 0x3FED #define codec_ctrl_reg 0x3FEE resetv: JUMP setup; NOP; NOP; NOP; irq2v: RTI; NOP; NOP; NOP; {interrupt vectors ...} hipwv: RTI;...
Page 178 8 Analog Interface Before autobuffering is enabled, separate circular buffers must be set up in data memory for the ADC receive and DAC transmit data. This is accomplished by selecting I (index) and M (modify) registers in the analog autobuffer/powerdown register; see Figure 8.5. Transmit data autobuffered to the DAC is addressed with the I register specified in the ATIREG field (bits 9, 10, 11).
Page 179 Analog Interface setup: I0 = ^buff1; {I0 points to first data buffer} L0 = %buff1; I1 = ^buff2; {I1 points to second data buffer} L1 = %buff2; M0 = 0x1; SI = 0x0; {initialize flag register} DM(flag_bit) = SI; {use I1 and M0 for tranmsit} {use I0 and M0 for receive} AY0 = 0x0203;...
Page 180: Circuit Design Considerations
8 Analog Interface CIRCUIT DESIGN CONSIDERATIONS The following sections discuss interfacing analog signals to the ADSP-21msp58/59. 8.5.1 Analog Signal Input Figure 8.6 shows the recommended input circuit for the ADSP-21msp58/59’s analog input pin (either VIN or VIN NORM The circuit of Figure 8.6 implements a first-order low pass filter (R The 3 dB point of the filter should be less than 40 kHz.
Page 181 Analog Interface and VIN are biased at the internal voltage reference NORM (nominally 2.5V) of the ADSP-21msp58/59, which allows the analog interface to operate from a single supply. The input signal should be ac-coupled with an external capacitor (C ). The value of C is determined by the input resistance of the analog input (VIN , VIN...
Page 182: Analog Signal Output
Figure 8.8 shows an example circuit which can be used to convert the differential output to a single-ended output. The circuit uses a differential-to-single-ended amplifier, the Analog Devices SSM-2141. ADSP-21msp5x VOUT VOUT Figure 8.7 Example Circuit For Differential Output With AC Coupling...
Page 183: Voltage Reference Filter Capacitance
Analog Interface ADSP-21msp5x +12 V 0.1 µF VOUT SSM-2141 VOUT N 0.1 µF –12 V Figure 8.8 Example Circuit For Single-Ended Output 8.5.3 Voltage Reference Filter Capacitance Figure 8.9 shows the recommended reference filter capacitor connections. The capacitor grounds should be connected to the same star ground point as that of Figure 8.6.
Page 184: Chapter 9 System Interface
System Interface OVERVIEW This chapter describes the basic system interface features of the ADSP-2100 family processors. The system interface includes various hardware and software features used to control the DSP processor. Processor control pins include a RESET signal, clock signals, flag inputs and outputs, and interrupt requests.
Page 185 System Interface XTAL CLKIN CLKOUT ADSP-21xx Figure 9.1 External Crystal Connections The internal phased lock loop of the processors generates an internal clock which is four times the instruction rate. The processors also generate a CLKOUT signal which is synchronized to the processors’...
Page 186: Synchronization Delay
System Interface CLKIN INTERNAL PROCESSOR PROCESSOR PROCESSOR STATE CYCLE CYCLE CLKOUT Figure 9.3 Clock Signals & Processor States (ADSP-2171, ADSP-2181, ADSP-21msp58/59) 9.2.1 Synchronization Delay Each processor has several asynchronous inputs (interrupt requests, for example), which can be asserted in arbitrary phase to the processor clock. The processor synchronizes such signals before recognizing them.
Page 187: Reset
System Interface Using a 1X or 1/2X frequency input clock with the phase-locked loop to generate the various internal clocks imposes certain restrictions. The CLKIN signal must be valid long enough to achieve phase lock before RESET can be deasserted. Also, the clock frequency cannot be changed unless the processor is in RESET.
Page 188: Software-Forced Rebooting
System Interface Processor Reboot Method Description ADSP-2101 Boot Force Setting the BFORCE bit in the System ADSP-2105 Control Register causes a reboot ADSP-2111 ADSP-2115 ADSP-2171 Boot Force Setting the BFORCE bit in the System Control Register causes a reboot Powerup Context Reset Setting the PUCR bit in the SPORT1 Autobuffer &...
Page 189 System Interface Control Field Description Reset Reboot Bus Exchange Register PX register undefined undefined Status Registers IMASK Interrupt service enables ASTAT Arithmetic status MSTAT Mode status unchanged SSTAT Stack status 0x55 0x55 ICNTL Interrupt control undefined unchanged Interrupt force/clear Control Registers (memory-mapped) BWAIT Boot memory wait states unchanged...
Page 190 System Interface Control Field Description Reset Reboot Bus Exchange Register PX register undefined undefined Status Registers IMASK Interrupt service enables ASTAT Arithmetic status MSTAT Mode status unchanged SSTAT Stack status 0x55 0x55 ICNTL Interrupt control undefined unchanged Interrupt force/clear Control Registers (memory-mapped) BWAIT Boot memory wait states unchanged...
Page 191 System Interface Control Field Description Reset Reboot Bus Exchange Register PX register undefined undefined Status Registers IMASK Interrupt service enables ASTAT Arithmetic status MSTAT Mode status unchanged SSTAT Stack status 0x55 0x55 ICNTL Interrupt control undefined unchanged Interrupt force/clear Control Registers (memory-mapped) BWAIT Boot memory wait states unchanged...
Page 192 System Interface Control Field Description Reset Reboot Bus Exchange Register PX register undefined undefined Status Registers IMASK Interrupt service enables ASTAT Arithmetic status MSTAT Mode status unchanged SSTAT Stack status 0x55 0x55 ICNTL Interrupt control undefined unchanged Interrupt force/clear Control Registers (memory-mapped) BWAIT Boot memory wait states unchanged...
Page 193 System Interface FO (SPORT1 only) Flag Out value undefined unchanged CLKODIS CLKOUT disable unchanged BIASRND MAC biased rounding unchanged Host Interface Port Registers (memory-mapped) HDR0-5 HIP data registers undefined used during HIP reboot HSR6 HIP status register 0x0000 used during HIP reboot HSR7 HIP status register 0x0080...
Page 194 System Interface Serial Port Control Registers (memory-mapped, one set per SPORT) ISCLK Internal serial clock unchanged RFSR, TFSR Frame sync required unchanged RFSW, TFSW Frame sync width unchanged IRFS, ITFS Internal frame sync unchanged INVRFS, INVTFS Invert frame sense unchanged DTYPE Companding type, format unchanged...
Page 195 System Interface Control Field Description Reset Reboot Bus Exchange Register PX register undefined undefined Status Registers IMASK Interrupt service enables ASTAT Arithmetic status MSTAT Mode status unchanged SSTAT Stack status 0x55 0x55 ICNTL Interrupt control undefined unchanged Interrupt force/clear Control Registers (memory-mapped) BWAIT Boot memory wait states unchanged...
Page 196: Adsp-2181 Register Values For Bdma Booting
System Interface FO (SPORT1 only) Flag Out value undefined unchanged CLKODIS CLKOUT disable unchanged BIASRND MAC biased rounding unchanged Host Interface Port Registers (memory-mapped) HDR0-5 HIP data registers undefined used during HIP reboot HSR6 HIP status register 0x0000 used during HIP reboot HSR7 HIP status register 0x0080...
Page 197: External Interrupts
System Interface EXTERNAL INTERRUPTS Each ADSP-2100 family processor has a number of prioritized, individually maskable external interrupts which can be either level- or edge-triggered. These interrupt request pins are named IRQ0, IRQ1, and IRQ2. The IRQ0 and IRQ1 pins are only available as the (optional) alternate configuration of SPORT1.
Page 198: Flag Pins
System Interface associated with both external interrupt request lines and internal interrupts. If an interrupt occurs during a waitstated external memory access or during the extra cycles required to execute an instruction that accesses external memory more than once, it is not recognized between the cycles, only before or after. Edge-sensitive interrupts are latched, but not serviced, during bus grant (BG) unless the GO mode is enabled.
Page 199 System Interface (counter expired), the counter is not decremented as in other IF CE instructions. Flag outputs FL0, FL1 and FL2 are set to 1 at RESET. The Flag Out (F0) is not affected by RESET. The ADSP-2181 has eight additional general-purpose flag pins, PF7-0. These flags can be programmed as either inputs or outputs;...
Page 200: Powerdown
System Interface Programmable Flag Data DM(0x3FE5) PFDATA Figure 9.5 Programmable Flag Data Register (ADSP-2181) POWERDOWN The ADSP-2171, ADSP-2181, and ADSP-21msp58/59 provide a powerdown feature that allows the processor to enter a very low power dormant state through hardware or software control. In this CMOS standby state, power consumption is less than 1 mW (approximate).
Page 201: Powerdown Control
System Interface Even though the processor is put into the powerdown mode, the lowest level of power consumption still might not be achieved if certain guidelines are not followed. Lowest possible power consumption requires no additional current flow through processor output pins and no switching activity on active input pins.
Page 202: Entering Powerdown
System Interface 9.7.2 Entering Powerdown The powerdown sequence is defined as follows. 1.) Initiate the powerdown sequence by applying a high-to-low transition to the PWD pin or by setting the powerdown force control bit (PDFORCE) in the SPORT1 Autobuffer/Powerdown Control Register. 2.) The processor vectors to the non-maskable powerdown interrupt vector at address 0x002C.
Page 203: Exiting Powerdown
System Interface 9.7.3 Exiting Powerdown The powerdown mode can be exited with the use of the PWD pin or with RESET. There are also several user-selectable modes for start-up from powerdown which specify a start-up delay as well as specify the program flow after start-up.
Page 204: Ending Powerdown With The Reset Pin
System Interface 9.7.3.2 Ending Powerdown With The RESET Pin If RESET is asserted while the processor is in the powerdown mode, the processor is reset and instructions are executed from address 0x0000. A boot is performed if the MMAP pin is set to 0. If the RESET pin is used to exit powerdown, then it must be held low for the appropriate number of cycles.
Page 205 System Interface If the external clock is unstable when the processor exits powerdown, then the XTALDELAY control bit can be used. This allows time for the external clock to stabilize by inserting an additional 4096-cycle delay before the processor starts to execute instructions. The start-up delay can only be used when the processor is taken out of powerdown mode with the PWD pin.
Page 206: Operation During Powerdown
System Interface Depending on the particular situation and external system conditions, the powerdown modes shown above could be set conditionally. If you want to powerdown for a long time you may want to set the mode for lowest power consumption. If you want to powerdown for a short time, lowest power consumption may not be that important.
Page 207: Hip During Powerdown
System Interface If an external serial clock and an external frame sync signal are supplied, data can be clocked into the RX register or out of the TX register during powerdown. Since the TX register can not be updated while the processor is in powerdown, the same value is repeatedly clocked out the serial port.
Page 208: Idma Port During Powerdown (Adsp-2181)
System Interface While in powerdown, the processor can be reset by writing the HSR software reset bit. This will produce the same results as asserting the RESET pin for five cycles (minimum RESET pulse) on the processor. If an external crystal is used and the clock has been stopped, this reset duration is too short;...
Page 209: Bdma Port During Powerdown (Adsp-2181)
System Interface 9.7.5.5 BDMA Port During Powerdown (ADSP-2181) Do not powerdown the ADSP-2181 during a BDMA transfer. If you do, the DSP will not be able to recover correctly from powerdown and the contents of memory accessed by the ADSP-2181’s BDMA port will be corrupted. If you need to go into powerdown mode, either: •...
Page 210 System Interface load current will increase power dissipation. Some pins will be in one of several states depending upon the connection of mode pins. For example, the ADSP-2171’s HIP data bus pins may be either active or inactive depending whether a host write is in progress or how the host mode pins are connected.
Page 211 System Interface Direction State During Powerdown SCLK1 Active SCLK1 Driven to a static level if internal, high impedance otherwise TFS1/IRQ1 Active if SPORT 1 is enabled or configured alternate (IRQ1) TFS1 Driven if SPORT 1 is enabled and configured for internal transmit framing, high impedance otherwise RFS1/IRQ0 Active if SPORT 1 is enabled or configured alternate (IRQ0)
Page 212: Pwdack Pin
System Interface 9.7.7 PWDACK Pin The powerdown acknowledge pin (PWDACK) is an output that indicates when the processor is powered down. This pin is driven high by the processor when it has powered down and is driven low when the processor has completed its powerup sequence.
Page 213: Using Powerdown As A Non-Maskable Interrupt
System Interface When powerdown is terminated with the RESET pin or if a start-up delay is selected, a low level on the PWDACK pin only indicates the start of oscillations on the CLKOUT pin. It will not necessarily indicate the start of instruction execution.
Page 214: Chapter 10 Memory Interface
Memory Interface 10.1 OVERVIEW The ADSP-2100 family has a modified Harvard architecture in which data memory stores data and program memory stores both instructions and data. Each processor contains on-chip RAM and/or ROM, so that a portion of the program memory space and a portion of the data memory space reside on-chip.
Page 215 10 Memory Interface This chapter includes example timing diagrams for the memory interfaces of the ADSP-21xx processors. For each bus transaction, only the sequence of events is described; you must consult the processor data sheets for actual timing parameters. All timing diagrams use CLKOUT as a reference, which indicates the instruction execution rate.
Page 216: Program Memory Interface
Memory Interface 10.2 PROGRAM MEMORY INTERFACE This section describes the program memory interface of all ADSP-21xx processors except the ADSP-2181. The processors address 16K of 24-bit wide program memory, up to 2K on-chip and the remainder external, using the control lines shown in Figure 10.1.
Page 217 10 Memory Interface CLKIN CLKOUT Address Data Data External Program/Data Memory Read/Write PWAIT=0, DWAIT=0 (no wait states added) Figure 10.2A Memory Read And Write, No Wait States CLKIN CLKOUT Address Data Data External Program/Data Memory Read/Write PWAIT=1, DWAIT=1 (one wait state added) Figure 10.2B Memory Read And Write, One Wait State 10 –...
Page 218: Program Memory Maps
Memory Interface The program memory interface can generate 0 to 7 wait states for external memory devices. The program memory wait state field (PWAIT) in the system control register is shown in Figure 10.3. PWAIT defaults (after RESET ) to seven wait states for program memory accesses. System Control Register 0x3FFF PWAIT...
Page 219: Rom Program Memory Maps
10 Memory Interface ADSP-2101 ADSP-2111 ADSP-2105 ADSP-2171 ADSP-2115 ADSP-21msp58 0x0000 0x0000 0x0000 0x0000 INTERNAL RAM INTERNAL Loaded From External Loaded From Boot Memory 0x03FF External 0x0400 EXTERNAL Boot Memory 0x07FF Reserved 0x0800 EXTERNAL 0x07FF 0x0800 0x37FF 0x3800 INTERNAL RAM EXTERNAL EXTERNAL 0x37FF 0x3800...
Page 220 Memory Interface 0000 0000 0000 2K Internal RAM 2K Internal RAM 2K External Not Booted Booted 07FF 07FF 07FF 0800 0800 0800 8K Internal ROM 8K Internal ROM (ROMENABLE = 1) (ROMENABLE = 1) 8K Internal ROM (ROMENABLE Defaults to 1 During RESET) 8K External 8K External (ROMENABLE = 0)
Page 221 10 Memory Interface When the MMAP and BMODE pins both are set to 1, the ADSP-2172 (or ADSP-21msp59) will operate in standalone ROM execution mode. When MMAP=1 and BMODE=1, the ROM is automatically enabled and execution begins from program memory location 0x0800 at the start of ROM.
Page 222 Memory Interface 0x0000 0x0000 0x0000 0x0000 EXTERNAL EXTERNAL 0x07FF 0x07FF INTERNAL INTERNAL 0x0800 0x0800 INTERNAL INTERNAL 0x0FF0 0x0FF0 0x1FF0 0x1FF0 Reserved Reserved 0x0FFF 0x0FFF Reserved Reserved 0x1FFF 0x1FFF 0x1000 0x1000 0x2000 0x2000 EXTERNAL EXTERNAL EXTERNAL EXTERNAL 0x37FF 0x37FF 0x3800 0x3800 INTERNAL INTERNAL 0x3FFF...
Page 223: Data Memory Interface
10 Memory Interface 10.3 DATA MEMORY INTERFACE This section describes the data memory interface of all ADSP-21xx processors except the ADSP-2181. The processors supply a 14-bit address on the data memory address bus (DMA) which is multiplexed off-chip. Data is transferred across the upper 16 bits of the 24-bit memory data bus, which is also multiplexed off-chip.
Page 224: Data Memory Maps
Memory Interface 10.3.2 Data Memory Maps The processors can address a total of 16K words of 16-bit data memory. On-chip data memory is 1K in size and starts at address 0x3800 on the ADSP-2101 and ADSP-2111. On-chip data memory is 512 locations in size on the ADSP-2105 and ADSP-2115, again starting at address 0x3800.
Page 225 10 Memory Interface As shown in Figure 10.11, the ADSP-2101, ADSP-2111, ADSP-2105, ADSP-2115, and ADSP-2161/62/63/64 processors have five external wait state zones (DWAIT0–DWAIT4). Each of the five zones of external data memory has its own programmable number of wait states. Wait states are extra cycles that the processor either waits before latching data (on a read) or drives the data (on a write).
Page 226 Memory Interface 0x0000 1K External DWAIT0 0x0400 1K External DWAIT1 0x0800 EXTERNAL 6K External DWAIT2 0x2000 4K x 16 Internal INTERNAL 0x3000 4K x 16 Memory Mapped Registers and Reserved 0x3FFF Figure 10.13 Data Memory Map (ADSP-2165/66) The Data Memory Waitstate control register has a separate field for each zone of external memory.
Page 227: Memory-Mapped Peripherals
Some A/D and D/A converters require this type of interface. The .PORT directives in the System Builder and Assembler modules of the ADSP-2100 Family Development Software support this mapping.
Page 228: Boot Memory Interface
That is, a page length of 0 causes the boot address generator to generate byte addresses for 8 words which reside in 32 sequential ROM locations. The PROM Splitter utility, part of the ADSP-2100 Family Development Software tools, calculates the proper page length for your program and orders the bytes of your program as shown in Figure 10.16 (on the next...
Page 229: Powerup Boot & Software Reboot
10 Memory Interface Address 0000 Word 0: USB Word 0: MSB 0001 Word 0: LSB 0002 Page Length 0003 Word 1: USB 0004 Not Used 001B Word 7: USB 001C Word 7: MSB 001D Word 7: LSB 001E Not Used 001F Figure 10.16 EPROM Contents 10.4.2 Powerup Boot &...
Page 230: Boot Memory Access
Memory Interface System Control Register DM(0x3FFF) BFORCE (Boot Force Bit) BWAIT (Boot Wait States) Default=3 for ADSP-21xx Default=7 for ADSP-2171, ADSP-21msp58 BPAGE (Boot Page Select) Default = 0 Figure 10.17 Boot Control Fields In System Control Register 10.4.3 Boot Memory Access The processor can boot its internal memory from a single byte-wide CMOS EPROM, such as the 27C64 and 27C512.
Page 231 10 Memory Interface To execute the boot operation, the boot address generator generates the appropriate byte addresses and loads internal program memory with the contents of the EPROM. The internal program memory is loaded beginning with the high addresses. For example, assume that eight 24-bit words are loaded into the processor during the booting process.
Page 232 Memory Interface Byte Address Word Pointer 15 14 Counter Page # 8-Bit Page Length 2-bit byte code: USB = 00 MSB = 01 Figure 10.18 Boot Memory Address LSB = 10 15 14 Page # 8-Bit Page Length 1st Word Page # 8-Bit Page Length Page #...
Page 233 10 Memory Interface Address EPROM Order Addressed (bytes) 0000 Word 0: USB Word 0: MSB 0001 Word 0: LSB 0002 0003 Page Length Word 1: USB 0004 Word 1: MSB 0005 Word 1: LSB 0006 Not Used 0007 Word 6: USB 0018 2nd word loaded Word 6: MSB...
Page 234: Bus Request/Grant
Memory Interface 10.5 BUS REQUEST / GRANT This section describes the bus request and grant feature of all ADSP-21xx processors, including the ADSP-2181. The ADSP-21xx can relinquish control of its data and address buses to an external device. The external device requests the bus by asserting (low) the bus request signal, is an asynchronous input.
Page 235 10 Memory Interface The ADSP-2171 and ADSP-2181 processors have an additional feature, the Bus Grant Hung ( ) output, which lets them operate in a multiprocessor system with a minimum number of wasted cycles. The pin asserts when the ADSP-21xx is ready to execute an instruction but is stopped because the external bus is granted to another device.
Page 236: Adsp-2181 Memory Interfaces
ADSP-2181 MEMORY INTERFACES The ADSP-2181 has the same modified Harvard architecture for internal memory as the other processors of the ADSP-2100 family. In this architecture, Data Memory stores data values and Program Memory stores both instructions and data. The ADSP-2181 has as its full base memory on-chip: 16K x 24-bit words of internal program memory RAM and 16K x 16-bit words of internal data memory RAM.
Page 237 10 Memory Interface Figure 10.23 shows the external memory buses and control signals in an ADSP-2181 system. Two control lines determine the direction of external memory transfers: is active low signaling a read and is active low for a write operation. Typically, you would connect (Output Enable) and (Write Enable) of your memory.
Page 238: Adsp-2181 Program Memory Interface
Memory Interface Unlike other processors of the ADSP-2100 family, the ADSP-2181 supports several additional memory interfacing features. These features include: • External Overlay Memory in 8K segments: these segments can be swapped for the upper 8K of internal program memory or lower 8K of data memory.
Page 239 10 Memory Interface System Control Register DM (0x3FFF) SPORT0 Enable 1 = enabled, 0 = disabled SPORT1 Enable PWAIT 1 = enabled, 0 = disabled Program Memory Overlay Wait States SPORT1 Configure 1 = serial port 0 = FI, FO, IRQ0, IRQ1, SCLK Figure 10.24 PWAIT Field in System Control Register The on-chip program memory and overlays can hold instructions and data intermixed in any combination.
Page 240 Memory Interface MMAP = 0 MMAP = 1 Program Memory Address Program Memory Address 0x3FFF 0x3FFF 8K Internal (PMOVLAY = 0) 8K Internal (PMOVLAY = 0) External 8K (PMOVLAY = 1 or 2) 0x2000 0x2000 0x1FFF 0x1FFF 8K External 8K Internal 0x0000 0x0000 Figure 10.25 ADSP-2181 Program Memory Map...
Page 241 10 Memory Interface ADSP-2100 family processors. Figure 10.26 shows a memory design that provides full external program and data memory overlays for an ADSP-2181 processor, assuming that MMAP=0. The important points to note about this design are: • Three 32K x 8-bit SRAMs are required for full external program and data memory overlays;...
Page 242 Memory Interface DM Overlay 2 A13 = 1 PMS = 1 DM Overlay 1 A13 = 0 PM Overlay 2 A13 = 1 PMS = 0 PM Overlay 1 A13 = 0 Figure 10.27 Memory Overlay Addressing For Example Design There are some restrictions on using program memory overlays: •...
Page 243: Adsp-2181 Data Memory Interface
10 Memory Interface contents of PMOVLAY as part of your interrupt service routine. 10.6.2 ADSP-2181 Data Memory Interface The ADSP-2181 addresses 16K x 16-bit wide internal data memory and two 8K x 16-bit wide external data memory overlays. All accesses to internal data memory are completed in a single processor instruction cycle.
Page 244 Memory Interface includes four fields for the ADSP-2181’s I/O memory space. The Data Memory overlay select (DMOVLAY) register lets you choose a memory overlay to map from address DM(0x0000) to address DM(0x1FFF). The DMOVLAY register is unique to the ADSP-2181. The memory mapped to this space and corresponding DMOVLAY contents are shown in Figure 10.29.
Page 245: Adsp-2181 Byte Memory Interface
The ADSP-2181’s byte memory space is 8 bits wide and can address up to 4M bytes of program code or data. This memory space takes the place of the boot memory space found on other ADSP-2100 family processors. Unlike boot memory space, byte memory has read/write access through the ADSP-2181’s BDMA port.
Page 246 Memory Interface Control Register and the IOWAIT0-3 bit fields that control I/O memory waitstate regions. The Wait State Control Register is divided into the following fields: • IOWAIT0. This 3-bit field sets the number of waitstates (0-7) for accesses to I/O memory addresses 0x000–0x1FF. •...
Page 247 IDMA. This combination of the I/O memory and IDMA channels reduces system bus transfer rate limitations. Note: As with other ADSP-2100 Family processors, on the ADSP-2181 you can define memory-mapped I/O ports with the assembler’s .PORT directive. On the ADSP-2181, this directive defines memory-mapped I/O ports in external program memory overlays or data memory overlays.
Page 248: Adsp-2181 Composite Memory Select
Memory Interface labels to I/O memory addresses, use a #define macro. The best use of the .PORT directive is in porting non-ADSP-2181 applications to the ADSP-2181; otherwise, use I/O memory space for memory-mapped I/O. 10.6.5 ADSP-2181 Composite Memory Select The ADSP-2181 has a programmable memory select signal, Composite Memory Select ( ).
Page 249: External Memory Read - Overlays & I/O Memory
10 Memory Interface signal. In this system the line drives the chip select for all three SRAMs. This lets you use three 32K x 8-bit SRAMs, with no glue logic, for complete program and data memory overlays. 10.6.6 External Memory Read – Overlays & I/O Memory External memory reads may access either PM overlays, DM overlays, or I/O memory space.
Page 250: External Memory Write - Overlays & I/O Memory
Memory Interface IOMS external signals: , and remain high (deasserted), and the address and data buses are tristated. 10.6.7 External Memory Write – Overlays & I/O Memory External memory writes may access either PM overlays, DM overlays, or I/O memory space. These read operations occur in the following sequence (see Figure 10.35): 1) The ADSP-2181 executes a write to an external memory address;...
Page 251 10 Memory Interface Access Address Data Internal program high high high high high tristated tristated memory only Internal data high high high high high tristated tristated memory only Internal program high high DM address DM data memory, external (for (for data memory read) write)
Page 252: Chapter 11 Dma Ports
DMA Ports 11.1 OVERVIEW The ADSP-2181 supports several DMA interfacing features: • Byte Memory & Byte Memory DMA (BDMA): this memory space can address up to 4M bytes. The byte memory interface supports booting from and runtime access to inexpensive 8-bit memories. The BDMA feature lets you define the number of memory locations the ADSP-2181 will transfer to/from internal memory in the background while continuing foreground processing.
Page 253: Bdma Port
The ADSP-2181’s byte memory space is 8 bits wide and can address up to 4M bytes of program code or data. This memory space takes the place of the boot memory space found on other ADSP-2100 family processors. Unlike boot memory space, byte memory has read/write access through the ADSP-2181’s BDMA port.
Page 254 EPROM: • Develop the data/code to be accessed at runtime • Use the ADSP-2100 Family PROM Splitter utility to split the file into single page (or smaller) 16K x 8-bit-wide segments • Program these pages into your EPROM, noting the offset (page number) of each •...
Page 255: Bdma Port Functional Description
11 DMA Ports 11.2.1 BDMA Port Functional Description The BDMA Port lets you load (and store) program instructions and data from (and to) byte memory with very low processor overhead. While the ADSP-2181 is executing program instructions, the BDMA port reads (or writes) code or data from (or to) byte memory—stealing one ADSP-2181 cycle per word when it needs to write to (or read from) internal memory.
Page 256 DMA Ports BDMA Internal Address DM(0x3FE1) BIAD Figure 11.2 BDMA Internal Address Register BDMA External Address DM(0x3FE2) BEAD Figure 11.3 BDMA External Address Register 11 – 5...
Page 257 11 DMA Ports BDMA Control DM(0x3FE3) BTYPE (see table) BMPAGE BDIR 0 = load from BM 1 = store to BM BTYPE Internal Memory Space PM 0 = run during BDMA Word Size 1 = halt during BDMA, context reset when done Alignment full full...
Page 258 DMA Ports BCR can be set to: Allow program execution during BDMA Inhibit program execution during BDMA transfers and cause a context reset after transfer is complete BMPAGE lets you select the starting page for BDMA transfer. Note: Rebooting with BDMA Context Reset (BCR=1) is similar to a Powerup Context Reset.
Page 259 11 DMA Ports BDMA Word Count (MMAP=0 and BMODE=0) DM(0x3FE4) BWCOUNT BDMA Word Count (MMAP=1 or BMODE=1) DM(0x3FE4) BWCOUNT Figure 11.5 BDMA Word Count Register Programmable Flag & Composite Select Control DM(0x3FE6) BMWAIT PFTYPE 1 = Output CMSSEL 0 = Input 1 = Enable CMS 0 = Disable CMS Figure 11.6 BMWAIT Field (in Programmable Flag &...
Page 260: Byte Memory Word Formats
DMA Ports 11.2.3 Byte Memory Word Formats In your byte memory ROM or RAM, data is stored by the ADSP-21xx PROM Splitter according to the data format you select: 24-bit program memory words, 16-bit data memory words, 8-bit data memory bytes with MSB- alignment, or 8-bit data memory bytes with LSB-alignment.
Page 261 7. After the boot sequence is complete (32 words transferred), program execution begins at internal PM address 0x0000. The ADSP-2100 Family PROM Splitter utility provides a boot loader option for ADSP-2181 based designs; see “Development Software Features for BDMA Booting” below.
Page 262: Development Software Features For Bdma Booting
32 words; it continues to load from the Byte Port until your whole program is loaded. Refer to the ADSP-2100 Family Assembler Tools & Simulator Manual as well as the software release note for complete information on the PROM Splitter features.
Page 263: Idma Port
11 DMA Ports 11.3 IDMA PORT The IDMA Port of the ADSP-2181 is a parallel I/O port that lets the processor’s internal memory be read or written by a host system. The IDMA Port architecture eases host bus interface design. Think of the IDMA port as a gateway to all internal memory locations on the DSP (except for the processor’s memory-mapped control registers).
Page 264 DMA Ports Four IDMA port inputs control when the port is selected ( ) for read ), write ( ), or address latch (IAL) operations on its address/data bus (IAD0-15). The IDMA Port Select ( ) line acts as a chip select for all IDMA operations.
Page 265: Idma Port Functional Description
11 DMA Ports 11.3.2 IDMA Port Functional Description The IDMA Port lets a host system directly access internal ADSP-2181 memory locations (but not the memory-mapped control registers). Figure 11.8 shows a flow chart of the most general case for IDMA transfers. In the case shown in Figure 11.8, the host system starts an IDMA transfer IACK by checking the state of the...
Page 266 DMA Ports Host starts IDMA transfer. Host checks IACK control line to see if the DSP is "Busy". Host uses IS and IAL control lines to latch the DMA starting address (IDMAA) and PM/DM selection into the DSP's IDMA Control Register. The DSP also can set the starting address and memory destination.
Page 267: Modifying Control Registers For Idma
11 DMA Ports • Host writes to internal Program Memory take two IDMA writes (for a 24-bit word through a 16-bit port). If an IDMA address latch cycle or a ADSP-2181 write to the IDMA Control Register occurs after a first Program Memory write cycle, the IDMA port “loses”...
Page 268: Idma Timing
DMA Ports 11.3.4 IDMA Timing From the host system interface point of view, there are three IDMA port operations with critical timing parameters. These operations are: • latching the IDMA internal memory address, • reading from the IDMA port, and •...
Page 269: Long Read Cycle
11 DMA Ports Note: The IDMA starting address and destination memory type is available to the host and to the ADSP-2181 in the IDMA Control Register. For Data Memory accesses, the ADSP-2181 increments the address automatically after each IDMA read or write transfer (16-bit word). For Program Memory accesses, the ADSP-2181 increments the address automatically after each pair of IDMA read or write transfers (24-bit word).
Page 270 DMA Ports IACK PREVIOUS READ IAD15-0 DATA DATA Figure 11.10 IDMA Long Read Cycle Timing In the case of a Program Memory operation, the second IDMA port read cycle for a given internal 24-bit word does not require an internal memory access, does not wait for an instruction cycle boundary, and takes 1.5 or 2.5 cycles.
Page 271: Short Read Cycle
11 DMA Ports 11.3.4.3 Short Read Cycle The host reads the contents of a ADSP-2181 internal memory location using the IDMA short read cycle. The read cycle, shown in Figure 11.11, consists of the following steps: IACK 1. Host ensures that line is low.
Page 272: Long Write Cycle
DMA Ports IACK PREVIOUS IAD15-0 DATA Figure 11.11 IDMA Short Read Cycle Timing 11.3.4.4 Long Write Cycle The host writes the contents of an internal memory location using the IDMA long write cycle. The write cycle, shown in Figure 11.12, consists of the following steps: IACK 1.
Page 273 11 DMA Ports IACK IAD15-0 DATA Figure 11.12 IDMA Long Write Cycle Timing Note: IDMA port writes to Program Memory require two IDMA port write cycles to write a word to ADSP-2181 internal Program Memory. The ADSP-2181 acknowledges the IDMA port write of the first 16 bits (MSBs of PM word) as they are written to a temporary holding latch, not waiting for an instruction cycle boundary.
Page 274: Short Write Cycle
DMA Ports 11.3.4.5 Short Write Cycle The host writes the contents of a ADSP-2181 internal memory location using the IDMA short write cycle. The write cycle, shown in Figure 11.13, consists of the following steps: IACK 1. Host ensures that line is low.
Page 275: Boot Loading Through The Idma Port
11 DMA Ports Note: IDMA port writes to Program Memory require two IDMA port write cycles to write a word to ADSP-2181 internal Program Memory. The ADSP-2181 acknowledges the IDMA port write of the first 16 bits (MSBs of PM word) as they are written to a temporary holding latch, not waiting for an instruction cycle boundary.
Page 276: Dma Cycle Stealing, Dma Hold Offs, And Iack
DMA Ports IACK IACK IACK IACK IACK 11.3.6 DMA Cycle Stealing, DMA Hold Offs, and Acknowledge IACK signal is generated by the ADSP-2181 to signal that it is safe to IACK read or write through the IDMA port. After reset, is asserted (low).
Page 277 11 DMA Ports • SPORT Autobuffering to External Memory with Waitstated Access – When one of the processor’s serial ports needs to access external memory for autobuffering and the external access takes more than one cycle, the IDMA transfer will be held off. •...
Page 278: Chapter 12 Programming Model
Programming Model 12.1 OVERVIEW From a programming standpoint, the ADSP-21xx processors consist of three computational units, two data address generators, and a program sequencer, plus on-chip peripherals and memory that vary with each processor. Almost all operations using these architectural components involve one or more registers—to store data, to keep track of values such as pointers, or to specify operating modes, for example.
Page 279: Data Address Generators
12 Programming Model The ADSP-21xx registers are shown in Figure 12.1. Not all of these registers are available on every processor. The registers are grouped by function: data address generators (DAGs), program sequencer, computational units (ALU, MAC and shifter), bus exchange (PX), memory interface, timer, SPORTs, host interface and DMA interfaces.
Page 280 Programming Model Processor Core DATA ADDRESS GENERATORS DAG1 DAG2 (DM addressing only) (DM and PM addressing) Bit-reverse capability Indirect branch capability TIMER MEMORY INTERFACE 0x3FFD TPERIOD System Control 0x3FFF Register 0x3FFC TCOUNT Wait States 0x3FFE 0x3FFB TSCALE (ADSP-2181) SPORT 0 DMOVLAY PMOVLAY PROGRAM SEQUENCER...
Page 281: Program Sequencer
12 Programming Model 12.1.2 Program Sequencer Registers associated with the program sequencer control subroutines, loops, and interrupts. They also indicate status and select modes of operation. 12.1.2.1 Interrupts The ICNTL register controls interrupt nesting and external interrupt sensitivity; the IFC register lets you force and clear interrupts in software; the IMASK register masks (disables) individual interrupts.
Page 282: Status And Mode Bits
Programming Model 12.1.2.3 Status And Mode Bits The stack status (SSTAT) register contains full and empty flags for stacks. The arithmetic status (ASTAT) register contains status flags for the computational units. The mode status (MSTAT) register contains control bits for various options. MSTAT contains 4 bits that control alternate register selection for the computational units, bit-reverse mode for DAG1, and overflow latch and saturation modes for the ALU.
Page 283: Computational Units
12 Programming Model 12.1.3 Computational Units The registers in the computational units store data. The ALU and MAC require two inputs for most operations. The AX0, AX1, MX0 and MX1 registers store X inputs, and the AY0, AY1, MY0 and MY1 registers store Y inputs.
Page 284: Serial Ports
Programming Model 12.1.6 Serial Ports SPORT0 and SPORT1 each have receive (RX), transmit (TX) and control registers. The control registers are memory-mapped registers at locations 0x3FEF–0x3FFA in data memory. SPORT0 also has registers for controlling its multichannel functions. Each SPORT control register contains bits that control frame synchronization, companding, word length and, in SPORT0, multichannel options.
Page 285: Host Interface
ADSP-2111 with discussion of each part of the program. The program can also be executed on any other ADSP-21xx processor, with minor modifications. This FIR filter program demonstrates much of the conceptual power of the ADSP-2100 family architecture and instruction set. {ADSP-2111 FIR Filter Routine -serial port 0 used for I/O -internally generated serial clock -12.288 MHz processor clock rate is divided to 1.536 MHz serial clock...
Page 286 Programming Model {code starts here} {load interrupt vector addresses} JUMP restarter; NOP; NOP; NOP; {restart interrupt} RTI; NOP; NOP; NOP; {IRQ2 interrupt} RTI; NOP; NOP; NOP; {HIP write interrupt} RTI; NOP; NOP; NOP; {HIP read interrupt} RTI; NOP; NOP; NOP; {SPORT0 transmit int} JUMP fir_start;...
Page 287: Example Program: Setup Routine Discussion
12 Programming Model .CONST taps=15, taps_less_one=14; Listing 12.1 (cont.) Include File, Constants Initialization 12.2.1 Example Program: Setup Routine Discussion The setup and main loop routine performs initialization and then loops on the IDLE instruction to wait until the receive interrupt from SPORT0 occurs.
Page 288: Example Program: Interrupt Routine Discussion
Programming Model SPORT0 is set up to generate the serial clock internally at 1.536 MHz, based on a processor clock rate of 12.288 MHz. The RFS and TFS signals are both required and the RFS signal is generated internally at 8 kHz, while the TFS signal comes from the external device communicating with the processor.
Page 289 12 Programming Model The subroutine begins by loading the counter register (CNTR). The new sample is read from SPORT0’s receive data register, RX0, into the SI register; the choice of SI is of no particular significance. Then, the data is written into the data buffer.
Page 290: Chapter 13 Hardware Examples
As with any hardware design, it is important that timing information be carefully analyzed. Therefore, the data sheet for the particular ADSP-2100 family processor used should be used in addition to the information presented in this chapter. 13 – 1...
Page 291: Boot Loading From Host Using Bus Request
13 Hardware Examples 13.2 BOOT LOADING FROM HOST USING BUS REQUEST & GRANT All ADSP-2100 family processors that have internal program memory RAM support boot loading. With boot loading, the processor reads instructions from a byte-wide external memory device (usually an EPROM) over the memory interface and stores the instructions in the 24- bit wide internal program memory.
Page 292 Hardware Examples 5 kΩ RESET Host Microcontroller ADSP-21xx (Port Bits) 74LS74 PB10 Can Be Polled If Necessary PB0-7 D8-15 Figure 13.1 ADSP-21xx Booting From Host 13 – 3...
Page 293 13 Hardware Examples When a low-level signal at the D input is clocked into the flip-flop, the output is brought high, deasserting The bus request pin ( ) of the ADSP-21xx is used to stop and synchronize the booting process. The host releases bus request, causing the ADSP-21xx to read one byte of boot data.
Page 294: Serial Port To Codec Interface
ADSP-21xx). This sequence is described in the Chapter 10, “Memory Interface.” To create a file for booting, use the PROM Splitter utility of the ADSP-2100 Family Development Software. The PROM Splitter automatically organizes the bytes in the proper order for booting.
Page 295 13 Hardware Examples Figure 13.2 shows an industry standard µ-law companding codec connected to a serial port (in this case, SPORT0) on an ADSP-21xx processor. The codec’s analog input at VFXI+ is internally amplified by a gain which is controlled by the resistor combination at GSX and VFXI–. The gain is 20 x log (R1 + R2)/R2 in this case, 20 log 2.
Page 296 Hardware Examples The processor uses frame synchronization signals to tell the codec to send and receive data. To transmit data to the codec, it sends a TFS0 pulse to the FSR input of the codec and then outputs the eight bits on DT0 on the next eight serial clock periods.
Page 297: Serial Port To Dac Interface
ADSP-21xx processors can send data directly to a DAC (digital- to-analog converter) for conversion to an analog signal. Analog Devices’ AD766 is a DAC that requires no extra logic to interface to the SPORT. The AD766 receives 16-bit data words serially, MSB first, which it then converts to an analog signal.
Page 298 Hardware Examples SCLK Latches data into DAC Figure 13.4 SPORT To AD766 DAC Timing The configuration of the SPORT control registers for this application is shown in Figure 13.5. SPORT0 Control Register: 0x3FF6 SPORT1 Control Register: 0x3FF2 Word Length = 16 bits SCLK generated internally Data format = right justify, zero fill Transmit framing required...
Page 299: Serial Port To Adc Interface
DSP processor can operate on. The ADSP-21xx processors can receive data from an ADC directly through a serial port. Analog Devices’ AD7872 is an ADC that requires no extra logic to interface to the SPORT. The AD7872 converts an analog signal to 14-bit samples.
Page 300 Hardware Examples SCLK MSB (0) Figure 13.7 SPORT To AD7872 ADC Timing RFS is configured for the alternate framing mode, externally generated, with inverted (active low) logic. The SPORT must also be programmed for external serial clock and a serial word length of 16 bits. The configuration of the SPORT control register for this application is shown in Figure 13.8.
Page 301: Serial Port To Serial Port Interface
13 Hardware Examples 13.6 SERIAL PORT TO SERIAL PORT INTERFACE The serial ports provide a convenient way to transfer data between ADSP- 21xx processors without using external memory or the memory bus and without halting either processor. The serial ports are connected as shown in Figure 13.9—in this example, SPORT1 of processor #1 is connected to SPORT0 of processor #2.
Page 302: 80C51 Interface To Host Interface Port
Hardware Examples The autobuffering capability of the serial ports can be used in this configuration to transfer an entire buffer of data from the data memory space of one processor to the other’s, without interrupt overhead. The serial ports handshake automatically—when one processor writes its’ TX0 register, the data is automatically transmitted to the other processor’s RX0 register and an autobuffer cycle is generated.
Page 303 13 Hardware Examples To access one of the HIP registers, the 80C51 asserts ALE and outputs a 16-bit address, with the upper half on P2.0-2.7 and the lower half on HSEL P0.0-0.7. The upper half is decoded to select the HIP via , and the lower half selects the HIP register via HAD0-7.
Page 304: Chapter 14 Software Examples
OVERVIEW This chapter provides a brief summary of the development process that you use to create executable programs for the ADSP-2100 family processors. The summary is followed by a number of software examples that can give you an idea of how to write your own applications.
Page 305: System Development Process
14.2 SYSTEM DEVELOPMENT PROCESS The ADSP-2100 family of processors is supported by a complete set of development tools. Programming aids and processor simulators facilitate software design and debug. In-circuit emulators and demonstration boards help in hardware prototyping.
Page 306 = USER FILE OR HARDWARE = SOFTWARE DEVELOPMENT TOOL = HARDWARE DEVELOPMENT TOOL Figure 14.1 ADSP-2100 Family System Development Process assembly language. A module is a unit of assembly language comprising a main program, subroutine, or data variable declarations. C programmers write C language files and use the C compiler to create assembly code modules from them.
Page 307: Single-Precision Fir Transversal Filter
14 Software Examples relocatable (placed at an absolute address). The linker places non-relocatable code or data modules at the specified memory addresses, provided the memory area has the correct attributes. Relocatable objects are placed at addresses selected by the linker. The linker generates a memory image file containing a single executable program which may be loaded into a simulator or emulator for testing.
Page 308 Software Examples correspond to the forty-third filter tap. The subroutine that realizes the sum-of-products operation used in computing the transversal filter is shown in Listing 14.1. .MODULE fir_sub; FIR Transversal Filter Subroutine Calling Parameters I0 —> Oldest input data value in delay line L0 = Filter length (N) I4 —>...
Page 309: Cascaded Biquad Iir Filter
14 Software Examples 14.4 CASCADED BIQUAD IIR FILTER A second-order biquad IIR filter section is represented by the transfer function (in the z-domain): –1 –2 –1 –2 H(z) = Y(z)/X(z) = ( B )/( 1 + A where A and B are coefficients that determine the desired impulse response of the system H(z).
Page 310: Sine Approximation
SE, MX0, MX1, MY0, MR, SR Computation Time (with N even): ADSP-2101/2102: (8 x N/2) + 5 cycles ADSP-2100/2100A: (8 x N/2) + 5 + 5 cycles All coefficients and data values are assumed to be in 1.15 format .ENTRY biquad;...
Page 311 14 Software Examples quadrant. The routine that implements this sine approximation, accurate to within two LSBs, is shown in Listing 14.3. This routine accepts input values in 1.15 format. The coefficients, which are initialized in data memory in 4.12 format, have been adjusted to reflect an input value scaled to the maximum range allowed by this format.
Page 312: Single-Precision Matrix Multiply
Software Examples .VAR/DM sin_coeff[5]; .INIT sin_coeff : 0x3240, 0x0053, 0xAACC, 0x08B7, 0x1CCE; .ENTRY sin; sin: I3=^sin_coeff; {Pointer to coeff. buffer} AY0=0x4000; AR=AX0, AF=AX0 AND AY0; {Check 2nd or 4th quad.} IF NE AR=-AX0; {If yes, negate input} AY0=0x7FFF; AR=AR AND AY0; {Remove sign bit} MY1=AR;...
Page 313 14 Software Examples .MODULE matmul; Single-Precision Matrix Multiplication Z(i,j) = ∑ [X(i,k) × Y(k,j)] i=0 to R; j=0 to T X is an RxS matrix Y is an SxT matrix Z is an RxT matrix Calling Parameters I1 —> Z buffer in data memory L1 = 0 I2 —>...
Page 314: Radix-2 Decimation-In-Time Fft
Software Examples .ENTRY spmm; spmm: DO row_loop UNTIL CE; I5=I6; {I5 = start of Y} CNTR=M5; DO column_loop UNTIL CE; I0=I2; {Set I0 to current X row} I4=I5; {Set I4 to current Y col} CNTR=M1; MR=0, MX0=DM(I0,M0), MY0=PM(I4,M5); {Get 1st data} DO element_loop UNTIL CE;...
Page 315 14 Software Examples FFT, you change the value of these constants and the twiddle factors. The data buffers twid_real and twid_imag in program memory hold the twiddle factor cosine and sine values. The inplacereal, inplaceimag, inputreal and inputimag buffers in data memory store real and imaginary data values.
Page 316: Dit Fft Subroutine
Software Examples .INIT inplaceimag: <inputimag.dat>; .INIT groups: N_div_2; .INIT bflys_per_group: 2; .INIT node_space: 2; .INIT blk_exponent: 0; .INIT padding: 0,0,0,0; {Zeros after inplaceimag} .GLOBAL twid_real, twid_imag; .GLOBAL inplacereal, inplaceimag; .GLOBAL inputreal, inputimag; .GLOBAL groups, bflys_per_group, node_space, blk_exponent; .EXTERNAL scramble, fft_strt; CALL scramble;...
Page 317 14 Software Examples setup operations for the next stage. {1024 point DIT radix 2 FFT} {Block Floating Point Scaling} .MODULE fft; Calling Parameters inplacereal=real input data in scrambled order inplaceimag=all zeroes (real input assumed) twid_real=twiddle factor cosine values twid_imag=twiddle factor sine values groups=N/2 bflys_per_group=1 node_space=1...
Page 318 Software Examples SB=-2; {—————— STAGE 1 ——————} I0=^inplacereal; I1=^inplacereal + 1; I2=^inplaceimag; I3=^inplaceimag + 1; M2=2; CNTR=nover2; AX0=DM(I0,M0); AY0=DM(I1,M0); AY1=DM(I3,M0); DO group_lp UNTIL CE; AR=AX0+AY0, AX1=DM(I2,M0); SB=EXPADJ AR, DM(I0,M2)=AR; AR=AX0-AY0; SB=EXPADJ AR; DM(I1,M2)=AR, AR=AX1+AY1; SB=EXPADJ AR, DM(I2,M2)=AR; AR=AX1-AY1, AX0=DM(I0,M0); SB=EXPADJ AR, DM(I3,M2)=AR; AY0=DM(I1,M0);...
Page 319 14 Software Examples MODIFY(I3,M2); {I3 ->y1 of 1st grp in stage} DO group_loop UNTIL CE; I4=^twid_real; {I4 -> C of W0} I5=^twid_imag; {I5 -> (-S) of W0} CNTR=DM(bflys_per_group); {CNTR=bfly count} MY0=PM(I4,M4),MX0=DM(I1,M0); {MY0=C,MX0=x1 } MY1=PM(I5,M4),MX1=DM(I3,M0); {MY1=-S,MX1=y1} DO bfly_loop UNTIL CE; MR=MX0*MY1(SS),AX0=DM(I0,M0); {MR=x1(-S),AX0=x0} MR=MR+MX1*MY0(RND),AX1=DM(I2,M0);...
Page 320 Software Examples {bflys_per_group=bflys_per_group / 2} {———— LAST STAGE —————} I0=^inplacereal; I1=^inplacereal+nover2; I2=^inplaceimag; I3=^inplaceimag+nover2; CNTR=nover2; M2=DM(node_space); M4=1; I4=^twid_real; I5=^twid_imag; MY0=PM(I4,M4),MX0=DM(I1,M0); {MY0=C,MX0=x1} MY1=PM(I5,M4),MX1=DM(I3,M0); {MY1=-S,MX1=y1} DO bfly_lp UNTIL CE; MR=MX0*MY1(SS),AX0=DM(I0,M0); {MR=x1(-S),AX0=x0} MR=MR+MX1*MY0(RND),AX1=DM(I2,M0); {MR=(y1(C)+x1(-S)),AX1=y0} AY1=MR1,MR=MX0*MY0(SS); {AY1=y1(C)+x1(-S),MR=x1(C)} MR=MR-MX1*MY1(RND); {MR=x1(C)-y1(-S)} AY0=MR1,AR=AX1-AY1; {AY0=x1(C)-y1(-S), AR=y0-[y1(C)+x1(-S)]} SB=EXPADJ AR,DM(I3,M1)=AR; {Check for bit growth, y1=y0-[y1(C)+x1(-S)]} AR=AX0-AY0,MX1=DM(I3,M0),MY1=PM(I5,M4);...
Page 321: Bit-Reverse Subroutine
14.7.3 Bit-Reverse Subroutine The bit-reversal routine, called scramble, puts the input data in bit- reversed order so that the results will be in sequential order. This routine uses the bit-reverse capability of the ADSP-2100 family processors. .MODULE dit_scramble; Calling Parameters...
Page 322: Block Floating-Point Scaling Subroutine
Software Examples 14.7.4 Block Floating-Point Scaling Subroutine The bfp_adj routine checks the FFT output data for bit growth and scales the entire set of data if necessary. This check prevents data overflow for each stage in the FFT. The routine, shown in Listing 14.8, uses the exponent detection capability of the shifter.
Page 323 14 Software Examples AR=AX0-AY0,MX0=DM(I0,M1); {Check if SB=-1; Get 1st sample} IF EQ JUMP strt_shift; {If SB=-1, shift block data 1 bit} AX0=-2; {Set AX0 for block exponent update} MY0=H#2000; {Set MY0 to shift 2 bits right} strt_shift: CNTR=Ntimes2 - 1; {initialize loop counter} DO shift_loop UNTIL CE;...
Page 324: Quick List Of Instructions
QUICK LIST OF INSTRUCTIONS This chapter is a complete reference for the instruction set of the ADSP-2100 family. The instruction set is organized by instruction group and, within each group, by individual instruction. The list below shows all of the instructions and the reference page for each.
Page 325: Overview
Library Manual. These manuals provide a complete guide to the development software. The handbooks Digital Signal Processing Applications Using The ADSP-2100 Family, Volume 1 and Volume 2 present DSP applications programs with source code and discussion. The instruction set is tailored to the computation-intensive algorithms common in DSP applications.
Page 326: Instruction Types & Notation Conventions
15.3 INSTRUCTION TYPES & NOTATION CONVENTIONS The ADSP-2100 family instruction set is grouped into the following categories: • Computational: ALU, MAC, Shifter • Move •...
Page 327: Multifunction Instructions
15.4 MULTIFUNCTION INSTRUCTIONS Multifunction operations take advantage of the inherent parallelism of the ADSP-2100 family architecture by providing combinations of data moves, memory reads/memory writes, and computation, all in a single cycle. 15.4.1 ALU/MAC With Data & Program Memory Read...
Page 328 Instruction Set Reference The ADSP-2100 family processors can execute both data fetches and the multiplication/accumulation in a single-cycle. Typically, a loop of multiply/accumulates can be expressed in ADSP-21xx source code in just two program lines. Since the on-chip program memory of the ADSP-21xx...
Page 329: Data & Program Memory Read
15 Instruction Set Reference 15.4.2 Data & Program Memory Read This variation of a multifunction instruction is a special case of the multifunction instruction described above in which the computation is omitted. It executes only the dual operand fetch, as shown below: AX0=DM(I2,M0), AY0=PM(I4,M6);...
Page 330: Computation With Data Register Move
Instruction Set Reference that the result of the computation is written to memory when, in fact, the previous value of the register is what is written. There is no requirement that the same register be used in this way although this will usually be the case in order to pipeline operands to the computation.
Page 331 15 Instruction Set Reference Multifunction Instructions <ALU> * † = DM ( M0 ) , = PM ( M4 ); <MAC> * † = DM ( M0 ) , = PM ( M4 ); <ALU> * , dreg DM ( M0 ) ;...
Page 332: Alu, Mac & Shifter Instructions
Instruction Set Reference 15.5 ALU, MAC & SHIFTER INSTRUCTIONS This group of instructions performs computations. All of these instructions can be executed conditionally except the ALU division instructions and the Shifter SHIFT IMMEDIATE instructions. 15.5.1 ALU Group Here is an example of one ALU instruction, Add/Add with Carry: IF AC AR=AX0+AY0+C;...
Page 333: Mac Group
15 Instruction Set Reference [IF condition] constant [IF condition] TSTBIT n OF xop SETBIT n OF xop CLRBIT n OF xop TGLBIT n OF xop [IF condition] PASS constant [IF condition] – [IF condition] [IF condition] [IF condition] [IF condition] –...
Page 334: Shifter Group
Instruction Set Reference Table 15.4 gives a summary list of all MAC instructions. In this list, condition stands for all the possible conditions that can be tested and xop and yop stand for the registers that can be specified as input for the MAC. A complete list of the permissible xops and yops is given in the reference page for each instruction.
Page 335: Move: Read & Write
15 Instruction Set Reference The “SR OR” modifier (which is optional) logically ORs the result with the current contents of the SR register; this allows you to construct a 32-bit value in SR from two 16-bit pieces. “NORM” is the operator and “(HI)” is the modifier that determines whether the shift is relative to the HI or LO (16-bit) half of SR.
Page 336 Instruction Set Reference MOVE Instructions reg ; DM (<address>) ; dreg DM ( DM ( M0 ) dreg <data> DM (<address>) = reg; <data> ; dreg PM ( PM ( dreg; Table 15.6 MOVE Instructions 15 – 13...
Page 337: Program Flow Control
Table 15.7 Processor Registers: reg & dreg 15.7 PROGRAM FLOW CONTROL Program flow control on the ADSP-2100 family processors is simple but powerful. Here is an example of one instruction: IF EQ JUMP my_label; JUMP, of course, is a familiar construct from many other languages. My_label is any identifier you wish to use as a label for the destination jumped to.
Page 338 Instruction Set Reference Program Flow Control Instructions [IF condition] JUMP (I4) (I5) (I6) (I7) <address> FLAG_IN JUMP <address> ; NOT FLAG_IN [IF condition] CALL (I4) (I5) (I6) (I7) <address> FLAG_IN CALL <address> ; NOT FLAG_IN [IF condition] RTS ; [IF condition] RTI ;...
Page 339: Miscellaneous Instructions
15 Instruction Set Reference 15.8 MISCELLANEOUS INSTRUCTIONS There are several miscellaneous instructions. NOP is a no operation instruction. The PUSH/POP instructions allows you to explicitly control the status, counter, PC and loop stacks; interrupt servicing automatically pushes and pops some of these stacks. The Mode Control instruction enables and disables processor modes of operation: bit-reversal on DAG1, latching ALU overflow, saturating the ALU result register, choosing the primary or secondary register set, GO...
Page 340 Instruction Set Reference Miscellaneous Instructions NOP; [ PUSH ] STS [, POP CNTR] [, POP PC] [, POP LOOP] ; BIT_REV [ , ] AV_LATCH AR_SAT SEC_REG G_MODE M_MODE TIMER MODIFY ( [IF condition] FLAG_OUT [ , ] RESET TOGGLE ENA INTS ;...
Page 341: Extra Cycle Conditions
15 Instruction Set Reference 15.9 EXTRA CYCLE CONDITIONS All instructions execute in a single cycle except under certain conditions, as explained below. 15.9.1 Multiple Off-Chip Memory Accesses The data and address busses of the ADSP-21xx processors are multiplexed off-chip. Because of this, the processors can perform only one off-chip access per instruction in a single cycle.
Page 342: Instruction Set Syntax
Instruction Set Reference 15.10 INSTRUCTION SET SYNTAX The following sections describe instruction set syntax and other notation conventions used in the reference page of each instruction. 15.10.1 Punctuation & Multifunction Instructions All instructions terminate with a semicolon. A comma separates the clauses of a multifunction instruction but does not terminate it.
Page 343: Status Register Notation
15 Instruction Set Reference 15.10.3 Status Register Notation The following notation is used in the discussion of the effect each instruction has on the processors’ status registers: An asterisk indicates a bit in the status word that is changed by the execution of the instruction.
Page 344: Alu
ADD / ADD with CARRY Syntax: [ IF cond ] = xop + yop + yop + C + constant + constant + C Permissible xops Permissible yops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE Permissible constants (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32767 –2, –3, –5, –9, –17, –33, –65, –129, –257, –513, –1025, –2049, –4097, –8193, –16385, –...
Page 345 ADD / ADD with CARRY Instruction Format: Conditional ALU/MAC operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 COND AMF specifies the ALU or MAC operation, in this case: AMF = 10010 for xop + yop + C...
Page 346: Subtract X-Y/Subtract X-Y With Borrow
SUBTRACT X-Y / SUBTRACT X-Y with BORROW Syntax: [ IF cond ] – yop – yop + C–1 + C–1 – constant – constant + C–1 Permissible xops Permissible yops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE Permissible constants (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32767 –2, –3, –5, –9, –17, –33, –65, –129, –257, –513, –1025, –2049, –4097, –8193, –16385, –...
Page 347 SUBTRACT X-Y / SUBTRACT X-Y with BORROW Set if a carry is generated. Cleared otherwise. Instruction Format: Conditional ALU/MAC operation, Instruction type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 COND AMF specifies the ALU or MAC operation.
Page 348: Subtract Y-X/Subtract Y-X With Borrow
SUBTRACT Y-X / SUBTRACT Y-X with BORROW Syntax: [ IF cond ] = yop – xop + C – 1 –xop + C – 1 –xop + constant –xop + constant + C – 1 Permissible xops Permissible yops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE...
Page 349 SUBTRACT Y-X / SUBTRACT Y-X with BORROW Set if an arithmetic overflow occurs. Cleared otherwise. Set if a carry is generated. Cleared otherwise. Instruction Format: Conditional ALU/MAC Operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 COND AMF specifies the ALU or MAC operation.
Page 350: And, Or, Xor
AND, OR, XOR Syntax: [ IF cond ] constant Permissible xops Permissible yops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE Permissible constants (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32767 –2, –3, –5, –9, –17, –33, –65, –129, –257, –513, –1025, –2049, –4097, –8193, –16385, –...
Page 351 AND, OR, XOR Instruction Format: Conditional ALU/MAC Operation, Instruction Type 9: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 COND AMF specifies the ALU or MAC operation.
Page 352 TEST BIT, SET BIT, CLEAR BIT, TOGGLE BIT (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) Syntax: [ IF cond ] TSTBIT n OF xop SETBIT n OF xop CLRBIT n OF xop TGLBIT n OF xop Permissible xops Permissible conds (see Table 15.9) NE NEG NOT AC NOT MV...
Page 353 TEST BIT, SET BIT, CLEAR BIT, TOGGLE BIT (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) Set if the result equals zero. Cleared otherwise. Set if the result is negative. Cleared otherwise. Always cleared. Always cleared. Instruction Format: (xop constant) AND/OR/XOR Conditional ALU/MAC operation, Instruction Type 9: (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COND...
Page 354: Pass/Clear
PASS / CLEAR BO, CC, and YY specify the constant (see Appendix A, Instruction Coding). Syntax: [ IF cond ] PASS constant Permissible xops Permissible yops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE Permissible constants (all ADSP-21xx processors) –1, 0, 1 Permissible constants (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) 2, 3, 4, 5, 7, 8, 9, 15, 16, 17, 31, 32, 33, 63, 64, 65, 127, 128, 129, 255, 256, 257,...
Page 355 PASS / CLEAR operation (using any constant other than –1, 0, or 1) causes the ASTAT status flags to be undefined. The PASS constant operation (using any constant other than –1, 0, or 1) is only available on the ADSP-217x, ADSP-218x, and ADSP-21msp58/59 processors and may not be used in multifunction instructions.
Page 356: Negate
NEGATE Destination register COND: condition Xop: X operand BO, CC, and YY specify the constant (see Appendix A, Instruction Coding). Syntax: [ IF cond ] = – Permissible xops Permissible yops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE Example: IF LT AR = –...
Page 357: Not
Note that –xop is a special case of yop – xop, with yop specified to be 0. Destination register Yop: Y operand Xop: X operand COND: condition Syntax: [ IF cond ] Permissible xops Permissible yops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE...
Page 358: Absolute Value
ABSOLUTE VALUE AMF = 11011 for NOT xop operation. Destination register Yop: Y operand Xop: X operand COND: condition Syntax: [ IF cond ] = ABS xop ; Permissible xops Permissible conds (see Table 15.9) EQ LE NE NEG NOT AC GT POS GE AV NOT MV...
Page 359: Increment
INCREMENT Destination register Xop: X operand COND: condition Syntax: [ IF cond ] = yop + 1 ; Permissible yops Permissible conds (see Table 15.9) EQ LE NE NEG NOT AC GT POS GE AV NOT MV LT NOT AV NOT CE Example: IF GT AF = AF + 1;...
Page 360: Decrement
DECREMENT Destination register Yop: Y operand Xop: X operand COND: condition Syntax: [ IF cond ] = yop – 1 ; Permissible yops Permissible conds (see Table 15.9) EQ LE NE NEG NOT AC GT POS GE AV NOT MV LT NOT AV NOT CE Example:...
Page 361: Divide
DIVIDE Destination register Yop: Y operand Xop: X operand COND: condition Syntax: DIVS yop , xop ; DIVQ xop ; Permissible xops Permissible yops These instructions implement yop ÷ xop. There are two Description: divide primitives, DIVS and DIVQ. A single precision divide, with a 32-bit numerator and a 16-bit denominator, yielding a 16-bit quotient, executes in 16 cycles.
Page 362 DIVIDE The quotient bit generated on each execution of DIVS and DIVQ is the AQ bit which is written to the ASTAT register at the end of each cycle. The final remainder produced by this algorithm (and left over in the AF register) is not valid and must be corrected if it is needed.
Page 363: Generate Alu Status
GENERATE ALU STATUS (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) Xop: X operand Yop: Y operand Syntax: NONE = <ALU> ; <ALU> may be any unconditional ALU operation except DIVS or DIVQ.* Examples: NONE = AX0 – AY0; NONE = PASS SR0; Description: Perform the designated ALU operation, generate the ASTAT status flags, then discard the result value.
Page 364: Mac Multiply
MULTIPLY Xop: X operand Yop: Y operand Syntax: [ IF cond] = xop * yop (SS) (SU) (US) (UU) (RND) Permissible xops Permissible yops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE Examples: IF EQ MR = MX0 * MF (UU); xop * yop MF = SR0 * SR0 (SS);...
Page 365 MULTIPLY biased vs. unbiased rounding, see “Rounding Mode” in the “Multiplier/ Accumulator” section of Chapter 2, Computation Units. Status Generated: ASTAT: SS MV AQ AS AC AV AN AZ – – – – – – – Set on MAC overflow (if any of upper 9 bits of MR are not all one or zero).
Page 366: Multiply/Accumulate
MULTIPLY / ACCUMULATE Z: Destination register COND: condition Xop: X operand register Syntax: [ IF cond ] = MR + xop * yop (SS) (SU) (US) (UU) (RND) Permissible xops Permissible yops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE Examples:...
Page 367 MULTIPLY / ACCUMULATE rounding is unbiased, except on the ADSP-217x, ADSP-218x, and ADSP- 21msp58/59 processors, which offer a biased rounding mode. For a discussion of biased vs. unbiased rounding, see “Rounding Mode” in the “Multiplier/Accumulator” section of Chapter 2, Computation Units. Status Generated: ASTAT: SS MV AQ AS...
Page 368: Multiply/Subtract
MULTIPLY / SUBTRACT Z: Destination register COND: condition Xop: X operand register Syntax: [ IF cond ] = MR – xop * yop (SS) (SU) (US) (UU) (RND) Permissible xops Permissible yops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE Examples:...
Page 369 MULTIPLY / SUBTRACT rounding is unbiased, except on the ADSP-217x, ADSP-218x, and ADSP- 21msp58/59 processors, which offer a biased rounding mode. For a discussion of biased vs. unbiased rounding, see “Rounding Mode” in the “Multiplier/Accumulator” section of Chapter 2, Computation Units. Status Generated: ASTAT: SS MV AQ AS...
Page 370: Clear
CLEAR Z: Destination register COND: condition Xop: X operand register Syntax: [ IF cond ] = 0 ; Permissible conds (see Table 15.9) NOT AV NOT AC NOT MV NOT CE Example: IF GT MR = 0; Description: Test the optional condition and, if true, then set the specified register to zero.
Page 371: Transfer Mr
TRANSFER MR Note that this instruction is a special case of xop * yop, with yop set to zero. Destination register COND: condition Syntax: [ IF cond ] = MR [ (RND) ] ; Permissible conds (see Table 15.9) NOT AV NOT AC NOT MV NOT CE...
Page 372: Conditional Mr Saturation
CONDITIONAL MR SATURATION Note that this instruction is a special case of MR + xop * yop, with yop set to zero. Destination register COND: condition Syntax: IF MV SAT MR ; Description: Test the MV (MAC Overflow) bit in the Arithmetic Status Register (ASTAT), and if set, then saturate the lower-order 32 bits of the 40-bit MR register;...
Page 373: Shifter
SHIFTER ARITHMETIC SHIFT Syntax: [ IF cond ] SR = [SR OR] ASHIFT xop (HI) (LO) Permissible xops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE Example: IF LT SR = SR OR ASHIFT SI (LO); Description: Test the optional condition and, if true, then perform the designated arithmetic shift.
Page 374 SHIFTER ARITHMETIC SHIFT Instruction Format: Conditional Shift Operation, Instruction Type 16: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 COND Shifter Function 0 1 0 0 ASHIFT (HI)
Page 375: Logical Shift
SHIFTER LOGICAL SHIFT Syntax: [ IF cond ] SR = [SR OR] LSHIFT xop (HI) (LO) Permissible xops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE Example: IF GE SR = LSHIFT SI (HI) ; Description: Test the optional condition and, if true, then perform the designated logical shift.
Page 376 SHIFTER LOGICAL SHIFT Instruction Format: Conditional Shift Operation, Instruction Type 16: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 COND Shifter Function 0 0 0 0 LSHIFT (HI)
Page 377: Normalize
SHIFTER NORMALIZE Syntax: [ IF cond ] SR = [SR OR] NORM xop (HI) (LO) Permissible xops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE Example: SR = NORM SI (HI) ; Description: Test the optional condition and, if true, then perform the designated normalization.
Page 378 SHIFTER NORMALIZE Instruction Format: Conditional Shift Operation, Instruction Type 16: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 COND Shifter Function 1 0 0 0 NORM (HI) 1 0 0 1...
Page 379: Derive Exponent
SHIFTER DERIVE EXPONENT Syntax: [ IF cond ] SE = EXP xop (HI ) (LO) (HIX) Permissible xops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE Example: IF GT SE = EXP MR1 (HI) ; Description: Test the optional condition and, if true, perform the designated exponent operation.
Page 380 SHIFTER DERIVE EXPONENT In the LO mode, the input is interpreted as the lower half of a double precision number. In performing the EXP operation on a double precision number, the higher half of the number must first be processed with EXP in the HI or HIX mode, and then the lower half can be processed with EXP in the LO mode.
Page 381: Block Exponent Adjust
SHIFTER BLOCK EXPONENT ADJUST Syntax: [ IF cond ] SB = EXPADJ xop ; Permissible xops Permissible conds (see Table 15.9) NOT AC NOT MV NOT AV NOT CE Example: IF GT SB = EXPADJ SI ; Description: Test the optional condition and, if true, perform the designated exponent operation.
Page 382 SHIFTER BLOCK EXPONENT ADJUST Instruction Format: Conditional Shift Operation, Instruction Type 16: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 COND SF = 1111.
Page 383: Arithmetic Shift Immediate
SHIFTER ARITHMETIC SHIFT IMMEDIATE Syntax: SR = [SR OR] ASHIFT xop BY <exp> (HI) (LO) Permissible xops <exp> Any constant between –128 and 127* Example: SR = SR OR ASHIFT SR0 BY 3 (LO); {do not use “+3”} Description: Arithmetically shift the bits of the operand by the amount and direction specified by the constant in the exponent field.
Page 384 SHIFTER ARITHMETIC SHIFT IMMEDIATE Instruction Format: Shift Immediate Operation, Instruction Type 15: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 <exp> Shifter Function 0 1 0 0 ASHIFT (HI) 0 1 0 1 ASHIFT (HI, OR)
Page 385: Logical Shift Immediate
SHIFTER LOGICAL SHIFT IMMEDIATE Syntax: SR = [SR OR] LSHIFT xop BY <exp> (HI) (LO) Permissible xops <exp> Any constant between –128 and 127* Example: SR = LSHIFT SR1 BY –6 (HI) ; Description: Logically shifts the bits of the operand by the amount and direction specified by the constant in the exponent field.
Page 386: Move
MOVE REGISTER MOVE Syntax: reg = reg ; Permissible registers CNTR OWRCNTR(write only) ASTAT MSTAT I0-I7 SSTAT(read only) TX0 M0-M7 IMASK L0-L7 ICNTL IFC(write only) Example: I7 = AR; Description: Move the contents of the source to the destination location. The contents of the source are always right-justified in the destination location after the move.
Page 387 MOVE REGISTER MOVE Instruction Format: Internal Data Move, Instruction Type 17: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEST SOURCE SRC RGP (Source Register Group) and SOURCE REG (Source Register) select the source register according to the Register Selection Table (see Appendix A).
Page 388: Load Register Immediate
MOVE LOAD REGISTER IMMEDIATE Syntax: reg = <data> ; dreg = <data> ; data: <constant> ‘%’ <symbol> ‘^’ <symbol> Permissible registers dregs (Instruction Type 6) regs (Instruction Type 7) (16-bit load) (maximum 14-bit load) CNTR OWRCNTR (write only) ASTAT MSTAT RX1 IMASK ICNTL I0-I7...
Page 389 MOVE LOAD REGISTER IMMEDIATE Instruction Format : Load Data Register Immediate, Instruction Type 6: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA DREG DATA contains the immediate value to be loaded into the Data Register destination location.
Page 390: Data Memory Read (Direct Address)
MOVE DATA MEMORY READ (Direct Address) Syntax: reg = DM ( <addr> ) ; Permissible registers CNTR OWRCNTR (write only) ASTAT MSTAT I0-I7 M0-M7 IMASK L0-L7 ICNTL IFC(write only) Example: SI = DM( ad_port0 ); Description: The Read instruction moves the contents of the data memory location to the destination register.
Page 391: Data Memory Read (Indirect Address)
MOVE DATA MEMORY READ (Indirect Address) Syntax: dreg = DM ( Permissible dregs Example: AY0 = DM (I3, M1); Description: The Data Memory Read Indirect instruction moves the contents of the data memory location to the destination register. The addressing mode is register indirect with post-modify. For linear (i.e. non-circular) indirect addressing, the L register corresponding to the I register used must be set to zero.
Page 392: Program Memory Read (Indirect Address)
MOVE PROGRAM MEMORY READ (Indirect Address) Syntax: dreg = PM ( Permissible dregs Example: MX1 = PM (I6, M5); Description: The Program Memory Read Indirect instruction moves the contents of the program memory location to the destination register. The addressing mode is register indirect with post-modify. For linear (i.e. non-circular) indirect addressing, the L register corresponding to the I register used must be set to zero.
Page 393: Data Memory Write (Direct Address)
MOVE DATA MEMORY WRITE (Direct Address) Syntax: DM ( <addr> ) = reg ; Permissible registers CNTR ASTAT MSTAT I0-I7 SSTAT(read only) TX1 M0-M7 IMASK L0-L7 ICNTL Example: DM (cntl_port0 ) = AR; Description: Moves the contents of the source register to the data memory location specified in the instruction word.
Page 394: Data Memory Write (Indirect Address)
MOVE DATA MEMORY WRITE (Indirect Address) Syntax: DM ( dreg <data> data: <constant> ‘%’ <symbol> ‘^’ <symbol> Permissible dregs Example: DM (I2, M0) = MR1; Description: The Data Memory Write Indirect instruction moves the contents of the source to the data memory location specified in the instruction word.
Page 395 MOVE DATA MEMORY WRITE (Indirect Address) Instruction Format: ALU / MAC Operation with Data Memory Write, Instruction Type 4: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 DREG Data Memory Write, Immediate Data, Instruction Type 2:...
Page 396: Program Memory Write (Indirect Address)
MOVE PROGRAM MEMORY WRITE (Indirect Address) Syntax: PM ( ) = dreg ; Permissible dregs Example: PM (I6, M5) = AR; Description: The Program Memory Write Indirect instruction moves the contents of the source to the program memory location specified in the instruction word.
Page 397: I/O Space Read/Write
MOVE I/O SPACE READ/WRITE (ADSP-218x only) Syntax: IO (<addr>) = dreg ; I/O write dreg = IO (<addr>) ; I/O read <addr> is an 11-bit direct address value between 0 and 2047 Permissible dregs Examples: IO(23) = AX0; MY1 = IO(2047); Description: The I/O space read and write instructions are used to access the ADSP-218x’s I/O memory space.
Page 398: Program Flow
PROGRAM FLOW JUMP Syntax: [ IF cond ] JUMP (I4) (I5) (I6) (I7) <addr> Permissible conds (see Table 15.9) NOT AV NOT AC NOT MV NOT CE Example: IF NOT CE JUMP top_loop; {CNTR is decremented} Description: Test the optional condition and, if true, perform the specified jump.
Page 399: Call
PROGRAM FLOW CALL Syntax: [ IF cond ] CALL (I4) (I5) (I6) (I7) <addr> Permissible conds (see Table 15.9) NOT AV NOT AC NOT MV NOT CE Example: IF AV CALL scale_down; Description: Test the optional condition and, if true, then perform the specified call.
Page 400: Jump Or Call On Flag In Pin
PROGRAM FLOW JUMP or CALL ON FLAG IN PIN Syntax: FLAG_IN JUMP <addr> NOT FLAG_IN CALL Example: IF FLAG_IN JUMP service_proc_three; Description: Test the condition of the FI pin of the processor and, if set to one, perform the specified jump or call. If FI is zero then perform a no- operation.
Page 401: Modify Flag Out Pin
PROGRAM FLOW MODIFY FLAG OUT PIN Syntax: [ IF cond ] FLAG_OUT [, …] ; RESET TOGGLE Example: IF MV SET FLAG_OUT, RESET FL1; Description: Evaluate the optional condition and if true, set to one, reset to zero, or toggle the state of the specified flag output pin(s). Otherwise perform a no-operation and continue with the next instruction.
Page 402 PROGRAM FLOW Syntax: [ IF cond ] RTS ; Permissible conds (see Table 15.9) NOT AV NOT AC NOT MV NOT CE Example: IF LE RTS ; Description: Test the optional condition and, if true, then perform the specified return. If the condition is not true then perform a no-operation. Omitting the condition performs the return unconditionally.
Page 403 PROGRAM FLOW COND: condition Syntax: [ IF cond ] RTI ; Permissible conds (see Table 15.9) NOT AV NOT AC NOT MV NOT CE Example: IF MV RTI ; Description: Test the optional condition and, if true, then perform the specified return.
Page 404: Do Until
PROGRAM FLOW DO UNTIL COND: condition Syntax: DO <addr> [UNTIL term] ; Permissible terms FOREVER NOT AV NOT AC NOT MV Example: DO loop_label UNTIL CE ; {CNTR is decremented each pass through loop} Description: DO UNTIL sets up looping circuitry for zero-overhead looping.
Page 405 PROGRAM FLOW DO UNTIL Instruction Format: Do Until, Instruction Type 11: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Addr TERM ADDR specifies the address of the last instruction in the loop. In the Instruction Syntax, this field may be a program label or an immediate address value.
Page 406: Idle
PROGRAM FLOW IDLE Syntax: IDLE ; IDLE (n); Slow Idle Description: IDLE causes the processor to wait indefinitely in a low-power state, waiting for interrupts. When an interrupt occurs it is serviced and execution continues with the instruction following IDLE. Typically this next instruction will be a JUMP back to IDLE, implementing a low-power standby loop.
Page 407: Misc
MISC STACK CONTROL Syntax: [ PUSH STS ] [ , POP CNTR] [ , POP PC] [ , POP LOOP] ; Example: POP CNTR, POP PC, POP LOOP; Description: Stack Control pushes or pops the designated stack(s). The entire instruction executes in one cycle regardless of how many stacks are specified. The PUSH STS (Push Status Stack) instruction increments the status stack pointer by one to point to the next available status stack location;...
Page 408 MISC STACK CONTROL TOPPCSTACK A special version of the Register-to-Register Move instruction, Type 17, is provided for reading (and popping) or writing (and pushing) the top value of the PC stack. The normal POP PC instruction does not save the value popped from the stack, so to save this value into a register you must use the following special instruction: reg = TOPPCSTACK;...
Page 409 MISC STACK CONTROL Instruction Format: TOPPCSTACK=reg Internal Data Move, Instruction Type 17: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 SRC 1 1 1 1 SOURCE SRC RGP (Source Register Group) and SOURCE REG (Source Register) select the source register according to the Register Selection Table (see Appendix A).
Page 410: Mode Control
MISC MODE CONTROL Syntax: BIT_REV [, …] ; AV_LATCH AR_SAT SEC_REG G_MODE M_MODE TIMER Example: DIS AR_SAT, ENA M_MODE; Description: Enables (ENA) or disables (DIS) the designated processor mode. The corresponding mode status bit in the mode status register (MSTAT) is set for ENA mode and cleared for DIS mode. At reset, MSTAT is set to zero, meaning that all modes are disabled.
Page 411 MISC MODE CONTROL The AR saturation mode bit, (AR_SAT), when set to 1, causes the AR register to saturate if an ALU operation causes an overflow, as described in Chapter 2, “Computation Units.” The MAC result placement mode (M_MODE) determines whether or not the left shift is made between the multiplier product and the MR register.
Page 412: Modify Address Register
MISC MODIFY ADDRESS REGISTER Syntax: MODIFY Example: MODIFY (I1, M1); Description: Add the selected M register (M ) to the selected I register ), then process the modified address through the modulus logic with buffer length as determined by the L register corresponding to the selected I register (L ), and store the resulting address pointer calculation in the selected I register.
Page 413: Nop
MISC Syntax: NOP ; Description: No operation occurs for one cycle. Execution continues with the instruction following the NOP instruction. Status Generated: None affected. Instruction Format: No operation, Instruction Type 30 (see Appendix A), as shown below: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 15 –...
Page 414: Interrupt Enable/Disable
MISC INTERRUPT ENABLE & DISABLE (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) Syntax: ENA INTS ; DIS INTS ; Description: Interrupts are enabled by default at reset. Executing the DIS INTS instruction causes all interrupts (including the powerdown interrupt) to be masked, without changing the contents of the IMASK register.
Page 415: Multifunction
MULTIFUNCTION COMPUTATION with MEMORY READ Syntax: <ALU> , dreg = DM ( I0 , <MAC> <SHIFT> PM ( I4 , Permissible dregs Description: Perform the designated arithmetic operation and data transfer. The read operation moves the contents of the source to the destination register.
Page 416 MULTIFUNCTION COMPUTATION with MEMORY READ Because of the read-first, write-second characteristic of the processor, using the same register as source in one clause and a destination in the other is legal. The register supplies the value present at the beginning of the cycle and is written with the new value at the end of the cycle.
Page 417 MULTIFUNCTION COMPUTATION with MEMORY READ Status Generated: All status bits are affected in the same way as for the single function versions of the selected arithmetic operation. <ALU> operation ASTAT: SS MV AQ AS AC AV AN AZ Set if result equals zero. Cleared otherwise. Set if result is negative.
Page 418 MULTIFUNCTION COMPUTATION with MEMORY READ Instruction Format: ALU/MAC operation with Data Memory Read, Instruction Type 4: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dreg ALU/MAC operation with Program Memory Read, Instruction Type 5: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
Page 419 MULTIFUNCTION COMPUTATION with REGISTER to REGISTER MOVE Syntax: <ALU> , dreg = dreg ; <MAC> <SHIFT> Permissible dregs Description: Perform the designated arithmetic operation and data transfer. The contents of the source are always right-justified in the destination register after the read. The computation must be unconditional.
Page 420 MULTIFUNCTION COMPUTATION with REGISTER to REGISTER MOVE results in an assembler warning, but assembles and executes exactly as the first form of the instruction. Note that reading example (2) from left to right may suggest that the MR1 register value is loaded into AX0 and then AX0 is used in the computation, all in the same cycle.
Page 421 MULTIFUNCTION COMPUTATION with REGISTER to REGISTER MOVE <MAC> operation ASTAT: SS MV AQ AS AC AV AN AZ Set if the accumulated product overflows the lower-order 32 bits of the MR register. Cleared otherwise. <SHIFT> operation ASTAT: SS MV AQ AS AC AV AN AZ Affected only when executing the EXP operation;...
Page 422 MULTIFUNCTION COMPUTATION with MEMORY WRITE Syntax: DM ( I0 , = dreg , <ALU> <MAC> <SHIFT> PM ( I4 , Permissible dregs Description: Perform the designated arithmetic operation and data transfer. The write operation moves the contents of the source to the specified memory location.
Page 423 MULTIFUNCTION COMPUTATION with MEMORY WRITE Because of the read-first, write-second characteristic of the processor, using the same register as destination in one clause and a source in the other is legal. The register supplies the value present at the beginning of the cycle and is written with the new value at the end of the cycle.
Page 424 MULTIFUNCTION COMPUTATION with MEMORY WRITE <MAC> operation ASTAT: SS MV AQ AS AC AV AN AZ Set if the accumulated product overflows the lower-order 32 bits of the MR register. Cleared otherwise. <SHIFT> operation ASTAT: SS MV AQ AS AC AV AN AZ Affected only when executing the EXP operation;...
Page 425 MULTIFUNCTION COMPUTATION with MEMORY WRITE Shift operation with Data Memory Write, Instruction Type 12: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dreg Shift operation with Program Memory Write, Instruction Type 13: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dreg Result register...
Page 426: Data & Program Memory Read
MULTIFUNCTION DATA & PROGRAM MEMORY READ Syntax: = DM ( I0 , = PM ( I4 , M4 ) ; Description: Perform the designated memory reads, one from data memory and one from program memory. Each read operation moves the contents of the memory location to the destination register.
Page 427 MULTIFUNCTION ALU / MAC with DATA & PROGRAM MEMORY READ Syntax: <ALU> , AX0 = DM ( I0 , M0 ) , AY0 = PM ( I4 , M4 ) ; <MAC> Description: This instruction combines an ALU or a MAC operation with a data memory read and a program memory read.
Page 428 MULTIFUNCTION ALU / MAC with DATA & PROGRAM MEMORY READ The same data register may be used as a source for the arithmetic operation and as a destination for the memory read. The register supplies the value present at the beginning of the cycle and is written with the value from memory at the end of the cycle.
Page 429 MULTIFUNCTION ALU / MAC with DATA & PROGRAM MEMORY READ <MAC> operation ASTAT: SS MV AQ AS AC AV AN AZ Set if the accumulated product overflows the lower-order 32- bits of the MR register. Cleared otherwise. Instruction Format: ALU/MAC with Data and Program Memory Read, Instruction Type 1: 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Program Destination register Data Destination register...
Page 430: Instruction Coding
Instruction Coding OPCODES This appendix gives a summary of the complete instruction set of the ADSP-2100 family processors. Opcode field names are defined at the end of the appendix. Any instruction codes not shown are reserved for future use. Type 1: ALU / MAC with Data & Program Memory Read...
Page 431 A Instruction Coding Type 6: Load Data Register Immediate 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA DREG Type 7: Load Non-Data Register Immediate 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type 8: ALU / MAC with Internal Data Register Move...
Page 432 Instruction Coding Type 10: Conditional Jump (Immediate Address) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR COND Type 11: Do Until 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR TERM Type 12:...
Page 433 A Instruction Coding Type 17: Internal Data Move 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dest Source Type 18: Mode Control 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Control codes: Secondary register bank Bit-reverse mode...
Page 434 Instruction Coding Type 22: Reserved 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 COND Type 23: DIVQ 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Type 24:...
Page 435 A Instruction Coding Type 29: I/O Memory Space Read/Write (ADSP-218x only) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR DREG Type 30: No Operation (NOP) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 Type 31:...
Page 436: Abbreviation Coding
Instruction Coding ABBREVIATION CODING ALU / MAC Function codes No operation 0 0 0 0 0 MAC Function codes X * Y (RND) 0 0 0 0 1 MR + X * Y (RND) 0 0 0 1 0 MR – X * Y (RND) 0 0 0 1 1 X * Y...
Page 437 A Instruction Coding see YY, CC, BO at the end of this appendix see YY, CC, BO at the end of this appendix COND Status Condition codes Equal 0 0 0 0 Not equal 0 0 0 1 Greater than 0 0 1 0 Less than or equal 0 0 1 1...
Page 438 Instruction Coding DREG Data Register codes 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1...
Page 439 A Instruction Coding Data Address Generator codes DAG1 DAG2 Index Register codes Loop Stack Pop codes No Change Modify Register codes Dual Data Fetch Program Memory Destination codes PC Stack Pop codes No Change A – 10...
Page 440 Instruction Coding Register codes Codes not assigned are reserved. RGP = ASTAT 0 0 0 0 MSTAT 0 0 0 1 SSTAT (read only) 0 0 1 0 IMASK 0 0 1 1 ICNTL 0 1 0 0 CNTR 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0...
Page 441 A Instruction Coding Shifter Function codes LSHIFT (HI) 0 0 0 0 LSHIFT (HI, OR) 0 0 0 1 LSHIFT (LO) 0 0 1 0 LSHIFT (LO, OR) 0 0 1 1 ASHIFT (HI) 0 1 0 0 ASHIFT (HI, OR) 0 1 0 1 ASHIFT (LO)
Page 442 Instruction Coding TERM Termination codes for DO UNTIL Not equal 0 0 0 0 Equal 0 0 0 1 Less than or equal 0 0 1 0 Greater than 0 0 1 1 Greater than or equal 0 1 0 0 Less than 0 1 0 1 NOT ALU Overflow...
Page 443 A Instruction Coding see YY, CC, BO below ALU/MAC Result Register codes Result register Feedback register YY, CC, BO ALU / MAC Constant codes (Type 9) (ADSP-217x, ADSP-218x, ADSP-21msp58/59 only) Constant (hex) Bit # 0001 bit 0 0002 bit 1 0004 bit 2 0008...
Page 444: Division Exceptions
Division Exceptions DIVISION FUNDAMENTALS The ADSP-2100 family processors’ instruction set contains two instructions for implementing a non-restoring divide algorithm. These instructions take as their operands twos-complement or unsigned numbers, and in sixteen cycles produce a truncated quotient of sixteen bits. For most numbers and applications, these primitives produce the correct results.
Page 445: Unsigned Division
B Division Exceptions The DIVS primitive is executed once, with the proper operands (ex. DIVS AY1, AX0) to compute the sign of the quotient. The sign bit of the quotient is determined by XORing (exclusive-or) the sign bits of each operand. The entire 32-bit dividend is shifted left one bit.
Page 446: Integer Division
The quotient produced by a divide with a negative divisor will generally be one LSB less than the correct result. The divide algorithm implemented on the ADSP-2100 family does not correctly compensate for the twos- complement format of a negative number, causing this inaccuracy.
Page 447: Unsigned Division Error
B Division Exceptions There is one case where this discrepancy does not occur. If the result of the division operation should equal 0x8000, then it will be correctly represented, and not be one LSB off. There are several ways to correct for this error. Before changing any code, however, you should determine if a one-LSB error in your quotient is a significant problem.
Page 448 Division Exceptions Since many applications do not require complete error checking, the code has been designed so you can remove tests that are not necessary for your project. This will decrease memory requirements, as well as increase execution speed. The module signed_div expects the 32-bit dividend to be stored in AY1&AY0, and the divisor in AX0.
Page 449 This module can be used to generate correct results when using the divide primitives of the ADSP-2100 family. The code is organized in sections. This entire module can be used to handle all error conditions, or individual sections can be removed to increase execution speed.
Page 450 Division Exceptions Return Values AR = 16-bit quotient MR0 = 16-bit remainder AV flag set if divide would overflow Altered Registers AX0, AX1, AR, AF, AY0, AY1, MR, MY0 Computation Time: 30 cycles .ENTRY signed_div, unsigned_div; signed_div: MR0=AY0,AF=AX0+AY1; {Take divisor’s absolute value} MR1=AY1, AR=ABS AX0;...
Page 451 B Division Exceptions do_divs: DIVS AY1, AR; DIVQ AR; {Compute sign of quotient} DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; DIVQ AR; recover_sign: MY0=AX0,AR=PASS AY0;...
Page 452: Numeric Formats
INTEGER OR FRACTIONAL The ADSP-2100 family supports both fractional and integer data formats, with the exception that the ADSP-2100 processor does not perform integer multiplication. In an integer, the radix point is assumed to lie to the right of the LSB, so that all magnitude bits have a weight of 1 or greater. This format is shown in Figure C.1, which can be found on the following page.
Page 453 C Numeric Formats • • • Weight –(2 Sign Signed Integer Radix Point • • • Weight Unsigned Integer Radix Point Figure C.1 Integer Format In a fractional format, the assumed radix point lies within the number, so that some or all of the magnitude bits have a weight of less than 1. In the format shown in Figure C.2, the assumed radix point lies to the left of the 3 LSBs, and the bits have the weights indicated.
Page 454: Binary Multiplication
In multiplication, however, the inputs can have different formats, and the result depends on their formats. The ADSP-2100 family assembly language allows you to specify whether the inputs are both signed, both unsigned, or one of each (mixed-mode).
Page 455: Fractional Mode And Integer Mode
In the integer mode, the left shift does not occur. This is the mode to use if both operands are integers (in the 16.0 format). The 32-bit multiplier result is in 32.0 format, also an integer. On the ADSP-2100 only, the integer mode C – 4...
Page 456: Block Floating-Point Format
40-bit accumulator, a right shift can correct the result. In all processors other than the ADSP-2100, fractional and integer modes are controlled by a bit in the MSTAT register. At reset, these processors default to the fractional mode, for compatibility with the ADSP-2100.
Page 457 C Numeric Formats can grow by these two bits (two orders of magnitude) before overflowing; thus, these bits are called guard bits. If it is known that a process will not cause any value to grow by more than these two bits, then the process can be run without loss of data.
Page 458: D.1 Interrupt Vector Addresses
INTERRUPT VECTOR ADDRESSES Tables D.1–D.6 show the interrupts and associated vector addresses for each processor of the ADSP-2100 family. Note that SPORT1 can be configured as either a serial port or as a collection of control pins including two external interrupt inputs, IRQ0 and IRQ1 .
Page 459: Interrupt Vector Addresses
Interrupt Vector Addresses Interrupt Source Interrupt Vector Address RESET startup 0x0000 IRQ2 0x0004 (highest priority) HIP Write (from Host) 0x0008 HIP Read (to Host) 0x000C SPORT0 Transmit 0x0010 SPORT0 Receive 0x0014 SPORT1 Transmit or IRQ1 0x0018 SPORT1 Receive or IRQ0 0x001C Timer 0x0020 (lowest priority)
Page 460 Interrupt Vector Addresses Interrupt Source Interrupt Vector Address RESET startup (or powerup w/PUCR=1) 0x0000 (highest priority) Powerdown (non-maskable) 0x002C IRQ2 0x0004 HIP Write (from Host) 0x0008 HIP Read (to Host) 0x000C SPORT0 Transmit 0x0010 SPORT0 Receive 0x0014 Analog (DAC) Transmit 0x0018 Analog (ADC) Receive 0x001C...
Page 461: E.1 Overview
Control/Status Registers OVERVIEW This appendix shows bit definitions for 1) the memory-mapped control registers and 2) other (non-memory-mapped) control and status registers of all ADSP-21xx processors. The memory-mapped registers are listed in descending address order. Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.
Page 462 E Control/Status Registers Processor Core DATA ADDRESS GENERATORS DAG1 DAG2 (DM addressing only) (DM and PM addressing) Bit-reverse capability Indirect branch capability TIMER MEMORY INTERFACE 0x3FFD TPERIOD System Control 0x3FFF Register 0x3FFC TCOUNT Wait States 0x3FFE 0x3FFB TSCALE (ADSP-2181) SPORT 0 DMOVLAY PMOVLAY PROGRAM SEQUENCER...
Page 463 Control/Status Registers Memory-Mapped Registers Waitstate Control Register DM(0x3FFE) DWAIT4 DWAIT3 DWAIT2 DWAIT1 DWAIT0 DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0 (ADSP-2181) (ADSP-2181) (ADSP-2181) (ADSP-2181) (ADSP-2181) ROM Enable (ADSP-2172, ADSP-21msp59) 1 = enable 0 = disable Timer Registers TPERIOD Period Register DM(0x3FFD) TCOUNT Counter Register DM(0x3FFC) DM(0x3FFB) TSCALE Scaling Register...
Page 464 E Control/Status Registers Memory-Mapped Registers SPORT0 Control Register (Not on ADSP-2105) DM(0x3FF6) Multichannel Enable SLEN (Serial Word Length – 1) ISCLK DTYPE Data Format Internal Serial Clock Generation 00=right justify, zero-fill unused MSBs RFSR 01=right justify, sign-extend into unused MSBs 10=compand using µ-law Receive Frame Sync Required 11=compand using A-law...
Page 465 Control/Status Registers Memory-Mapped Registers SPORT0 Autobuffer Control Register (Not on ADSP-2105) DM(0x3FF3) RBUF TIREG TMREG RIREG RMREG Receive Autobuffering Enable TBUF Transmit Autobuffering Enable BIASRND MAC Biased Rounding Control Bit (ADSP-2171, ADSP-2181, ADSP-21msp58/59 only) CLKODIS CLKOUT Disable Control Bit (ADSP-2171, ADSP-2181, ADSP-21msp58/59 only) SPORT0 SCLKDIV (Not on ADSP-2105) Serial Clock Divide Modulus...
Page 466 E Control/Status Registers Memory-Mapped Registers SPORT1 Control Register DM(0x3FF2) Flag Out (read-only) SLEN (Serial Word Length – 1) ISCLK DTYPE Data Format Internal Serial Clock Generation 00=right justify, zero-fill unused MSBs RFSR 01=right justify, sign-extend into unused MSBs 10=compand using µ-law Receive Frame Sync Required 11=compand using A-law RFSW...
Page 467 Control/Status Registers Memory-Mapped Registers SPORT1 Autobuffer Control Register (Not on ADSP-21msp5x) DM(0x3FEF) RBUF XTALDIS Receive Autobuffer Enable XTAL Pin Disable During Powerdown 1=disabled, 0=enabled TBUF (XTAL pin should be disabled when Transmit Autobuffer Enable no external crystal is connected) RMREG XTALDELAY Receive M register Delay Startup From Powerdown 4096 Cycles...
Page 468 E Control/Status Registers Memory-Mapped Registers (ADSP-21msp5x only) Analog Control Register DM(0x3FEE) ADC Offset ADC Input Gain (ADC PGA) ADC Input Gain (ADC PGA) ADC Input Multiplexer Select 1=AUX input, 0=NORM input DABY DAC High Pass Filter Bypass 1=bypass, 0=insert OG2, OG1, OG0 DAC Output Gain (DAC PGA) ADBY ADC High Pass Filter Bypass...
Page 469 Control/Status Registers Memory-Mapped Registers (ADSP-2171, ADSP-2111, HMASK Interrupt Mask Register ADSP-21msp5x only) DM(0x3FE8) Host HDR0 Write Host HDR1 Write Host HDR5 Read Host HDR2 Write Host HDR4 Read Host HDR3 Write Host HDR3 Read Host HDR4 Write Host HDR2 Read Host HDR5 Write Host HDR1 Read Host HDR0 Read...
Page 470 E Control/Status Registers Memory-Mapped Registers (ADSP-2171, ADSP-2111, HSR6 Status Register ADSP-21msp5x only) DM(0x3FE6) Host HDR0 Write Host HDR1 Write 21xx HDR5 Write Host HDR2 Write 21xx HDR4 Write Host HDR3 Write 21xx HDR3 Write Host HDR4 Write 21xx HDR2 Write Host HDR5 Write 21xx HDR1 Write 21xx HDR0 Write...
Page 471 Control/Status Registers Memory-Mapped Registers Programmable Flag & Composite Select Control (ADSP-2181 only) DM(0x3FE6) BMWAIT PFTYPE 1 = Output CMSSEL 0 = Input 1 = Enable CMS 0 = Disable CMS Programmable Flag Data (ADSP-2181 only) DM(0x3FE5) PFDATA E – 11 Default bit values at reset are shown;...
Page 472 E Control/Status Registers Memory-Mapped Registers (ADSP-2181 only) BDMA Control DM(0x3FE3) BTYPE (see table) BMPAGE BDIR 0 = load from BM 1 = store to BM BTYPE Internal Memory Space PM 0 = run during BDMA Word Size 1 = halt during BDMA, Alignment full full...
Page 473 Control/Status Registers Memory-Mapped Registers (ADSP-2181 only) BDMA External Address DM(0x3FE2) BEAD BDMA Internal Address (ADSP-2181 only) DM(0x3FE1) BIAD (ADSP-2181 only) IDMA Control DM(0x3FE0) IDMAD Destination memory type IDMAA 0=PM, 1=DM Starting address E – 13 Default bit values at reset are shown; if no value is shown, the bit is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written with zeros.
Page 474 E Control/Status Registers Non-Memory-Mapped Registers ASTAT SSTAT (read-only) SS MV AQ AS AC AV AN AZ PC Stack Empty ALU Result Zero PC Stack Overflow ALU Result Negative Count Stack Empty ALU Overflow Count Stack Overflow ALU Carry Status Stack Empty ALU X Input Sign Status Stack Overflow ALU Quotient...
Page 475 Control/Status Registers Non-Memory-Mapped Registers ADSP-2101 IMASK ADSP-2105 ADSP-2115 INTERRUPT ENABLES 1 = enable 0 = disable (mask) Timer SPORT1 Receive or IRQ0 SPORT1 Transmit or IRQ1 SPORT0 Receive (must be set to 0 for ADSP-2105) SPORT0 Transmit (must be set to 0 for ADSP-2105) IRQ2 ADSP-2101 IFC (write-only)
Page 476 E Control/Status Registers Non-Memory-Mapped Registers IMASK ADSP-2111 INTERRUPT ENABLES 1 = enable 0 = disable (mask) Timer SPORT1 Receive or IRQ0 IRQ2 SPORT1 Transmit or IRQ1 HIP Write SPORT0 Receive HIP Read SPORT0 Transmit E – 16...
Page 477 Control/Status Registers Non-Memory-Mapped Registers IMASK ADSP-2181 INTERRUPT ENABLES 1 = enable 0 = disable (mask) IRQ2 Timer IRQL1 SPORT1 Receive or IRQ0 IRQL0 SPORT1 Transmit or IRQ1 SPORT0 Transmit BDMA Interrupt SPORT0 Receive IRQE IFC (write-only) ADSP-2181 INTERRUPT FORCE BITS INTERRUPT CLEAR BITS IRQ2 Timer...
Page 478 E Control/Status Registers Non-Memory-Mapped Registers IMASK ADSP-2171 INTERRUPT ENABLES 1 = enable 0 = disable (mask) IRQ2 Timer HIP Write SPORT1 Receive or IRQ0 HIP Read SPORT1 Transmit or IRQ1 SPORT0 Transmit Software Interrupt 0 SPORT0 Receive Software Interrupt 1 IFC (write-only) ADSP-2171 INTERRUPT FORCE BITS...
Page 479 Control/Status Registers Non-Memory-Mapped Registers IMASK ADSP-21msp5x INTERRUPT ENABLES 1 = enable 0 = disable (mask) IRQ2 Timer HIP Write SPORT1 Receive or IRQ0 HIP Read SPORT1 Transmit or IRQ1 SPORT0 Transmit ADC Receive SPORT0 Receive DAC Transmit IFC (write-only) ADSP-21msp5x INTERRUPT FORCE BITS INTERRUPT CLEAR BITS IRQ2...
Page 480 E Control/Status Registers Processor Core DATA ADDRESS GENERATORS DAG1 DAG2 (DM addressing only) (DM and PM addressing) Bit-reverse capability Indirect branch capability TIMER MEMORY INTERFACE 0x3FFD TPERIOD System Control 0x3FFF Register 0x3FFC TCOUNT Wait States 0x3FFE 0x3FFB TSCALE (ADSP-2181) SPORT 0 DMOVLAY PMOVLAY PROGRAM SEQUENCER...
Page 481 Index 1.15 format ............2-2 ASTAT ........2-10, 2-13, 2-19, 2-24, µ-law ...........1-2, 5-15, 5-23 ........2-26, 2-36, 3-21, 3-24, 12-5 Autobuffer service ..........5-39 Autobuffer timing ..........5-37 Autobuffering ..5-3, 5-4, 5-26, 5-32, 5-38, 5-40, A-law ............1-2, 5-23 ........5-41, 8-1, 8-9, 8-10, 8-11, 8-12, A/D converter ....
Page 482 Index Branching ............. 3-1 BTYPE ..............11-9 D/A ..............10-14 Buffer length ............4-5 DAC ..............1-3 Bus exchange ....1-5, 1-8, 2-15, 4-1, 4-9, 12-6 DAC interface ............ 13-8 Bus grant (BG) ........... 3-18, 9-15 DAG1 ............1-7, 4-2, 12-2 Bus request (BR) ....5-38, 10-15, 10-21, 13-2 DAG2 ......
Page 483 Index EXP ..............2-33 HMD0 ............7-3, 7-4 EXPADJ .............. 2-29 HMD1 ..............7-4 Exponent compare logic ........2-22 Hold offs ............11-25 Exponent detector ......2-22, 2-26, 2-27 Host ............... 1-2 External address bus ........1-3, 1-8 Host data bus ............7-4 External clock ..........
Page 484 Index Interrupt service ......3-12, 3-14, 3-16, Mode control .......... 12-5, 15-16 ............3-18, 3-20, 5-39 Mode status register (MSTAT) ....3-12, 3-22 Interrupt vector ......3-11, 3-12, 3-13, Modify (M) registers ..4-1, 4-2, 4-3, 5-26, 5-28 ............ 3-14, D-1, D-2, D-3 Modulo addressing ........
Page 485 Index Operation during powerdown ....... 9-23 OR/PASS logic ......... 2-22, 2-24 Quotient format ..........2-12 Output enable ......... 10-3, 10-24 Output registers ..........1-7 Overflow (AV) ... 2-2, 2-5, 2-8, 2-9, 2-13, 2-26, 2-36 Overwrite bit ............. 9-24 R bus ......... 1-6, 2-15, 2-18, 2-22 Overwrite mode ...........
Page 486 Index Shifter arithmetic ..........2-3 Shifter array ............2-22 T1 interface ............5-31 Shifter input/output registers ......2-28 TCOUNT ....... 6-1, 6-2, 6-3, 6-4, 12-6 Shifter operations ..........2-28 TDV ..............5-32 Shifter sign ............2-26 Termination condition ......3-6, 3-10 SI register ..........