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EPPI Programming Model
NOTE:
The EPPI_FRAME, EPPI_VDLY, and
result, frame track errors and vertical windowing are not possible in this mode.
1. Configure GP 1 FS mode by setting the EPPI_CTL.XFRTYPE bit =b#11 and the EPPI_CTL.FSCFG bit
=b#01. An external device can provide the frame syncs or the EPPI can source the frame syncs.
2. Program the
EPPI_LINE
EPPI_FS1 signal to monitor the line track errors. Program the
register.
EPPI_HCNT
3. Program the
EPPI_HDLY
EPPI_FS1. For example, the start of frame.
4. Program the
EPPI_HCNT
5. Configure DMA to move the data to or from memory.
6. Enable DMA.
7. Enable the EPPI.
8. To program the EPPI in internal clock mode, follow the procedure above with the EPPI_CTL.ICLKGEN bit
=0. After enabling the EPPI, add a delay of 200 SCLK1_0 cycles (worst case) to ensure the EPPI FIFO be-
comes full. Then, switch to internal clock mode by setting the EPPI_CTL.ICLKGEN bit =1.
Data moves in or out of memory. A frame sync frames the data for every line.
Configuring Transfers in GP 2 FS Mode
GP 2 FS mode is useful for video applications that use two hardware synchronization signals, HSYNC and VSYNC.
The HSYNC connects to the EPPI_FS1 signal and VSYNC connects to the EPPI_FS2 signal.
1. Configure the EPPI to operate in GP 0 FS mode by setting the EPPI_CTL.XFRTYPE bit =b#11 and the
EPPI_CTL.FSCFG bit =b#10. An external device can provide the frame syncs or the EPPI can source the
frame syncs.
2. Program the
EPPI_FRAME
to the number of EPPI_FS1 signal assertions expected between the start of each frame sync. The EPPI uses
the value to monitor frame track errors. Program the
3. Program the
EPPI_LINE
the EPPI_FS1 signal to monitor line track errors. Program the
EPPI_HCNT
register.
4. Program the
EPPI_HDLY
EPPI_FS1 signal. (For example, the start of the line).
5. Program the
EPPI_HCNT
18–32
EPPI_VCNT
register to contain the number clock cycles expected between two assertions of the
register to contain the number of clock cycles to wait after the assertion of
register to contain the number of data samples to receive or transmit for each frame.
register to contain the number of expected lines per frame. The value can be equal
register to contain the number of clock cycles expected between two assertions of
register to configure the number of clock cycles to wait after the assertion of the
register to contain the number of data samples to receive or transmit for each line.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers have no effect in GP 1 FS mode. As a
EPPI_LINE
register before the
EPPI_FRAME
EPPI_LINE
register before the
register.
EPPI_VCNT
register before the
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