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Figure 9-3: Hsaio Parity Bit Mapping
During read operation, the parity bits become part of the syndrome equation. The new syndrome bits are now the
XOR values of the 13 or 14 data bits plus the respective stored parity bit. If any of the seven syndrome bits is set, an
error situation is detected. An OR gate cross of the 7 bits reports the error, without specifying the type of the error.
If a single parity bit failed, the new 7-bit syndrome has 1 bit that is set. If a single data bit failed, the new syndrome
has 3 bits that are set, because all three related parity bits fail. So, an XOR gate cross of all seven syndrome bits
detects a single-bit error, indicating that an odd number of syndrome bits is set.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
BIT POSITION
31
30
29
28
ENCODED DATA BITS
d24
d23
d22
d21
x
x
x
x
x
x
x
PARITY
x
BIT
COVERAGE
x
x
x
x
BIT POSITION
15
14
13
12
ENCODED DATA BITS
d8
d7
d6
d5
x
x
x
x
x
PARITY
BIT
x
COVERAGE
x
x
x
x
x
x
BIT POSITION
38
37
36
ENCODED DATA BITS
d31
d30
d29
d28
x
x
x
x
x
PARITY
x
x
x
BIT
COVERAGE
x
27
26
25
24
23
22
21
20
d20
d19
d18
d17
d16
d15
d14
d13
d12
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
11
10
9
8
7
6
5
4
d4
d3
d2
d1
d0
p6
p5
p4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
36
34
33
32
d27
d26
d25
p0
p1
x
x
p2
x
x
x
x
p3
x
x
x
p4
x
p5
x
x
p6
19
18
17
16
d11
d10
d9
p0
x
x
x
x
p1
x
p2
x
p3
x
x
p4
x
p5
x
x
x
p6
3
2
1
0
p3
p2
p1
p0
x
p0
x
p1
x
p2
x
p3
p4
p5
p6
Data Integrity
9–7
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