Analog Devices ADSP-SC58 Series Hardware Reference Manual page 221

RCU Functional Description
System Reset (by source)
Software can trigger the reset by writing to the
any of the generic reset inputs.
RCU Architectural Concepts
To understand the architecture of the RCU, it is important to consider the reset sources and how differing resets
affect the functional units of the processor.
The RCU provides the hardware that controls how all the functional units enter and exit reset. Differences in func-
tional requirements and clocking constraints define how reset signals are generated. For example, units in different
clock domains must enter reset asynchronously but exit reset in a deterministic way.
The program must guarantee that none of the reset functions put the system in an undefined state or cause resources
to stall. This functionality is important when only one of the cores is reset. The program must guarantee that there
is no pending system activity involving Core n before it is reset. For example, there must be no pending transactions
to core 0 when the core 0 is reset and vice-versa.
The RCU Reset Sources table defines how reset sources affect the different functional units.
Table 6-4: RCU Reset Sources
Reset Source
SYS_HWRST pin assertion
SYSCLK clock domain system
reset by fault unit (FMU) or
TRU master
RCU_CTL.SYSRST bit set
(software triggered reset)
RCU_CRCTL.CR[n] bit set
(software triggered reset)
RCU Status and Error Signals
The RCU_STAT register reflects status and error information. There are three kinds of errors that can occur in the
RCU. The reset out error is triggered when RSTOUT is both asserted and deasserted at the same time. The lock
6–4
RCU_CTL
Reset Type Affected Functional Units
Hardware Reset All functional units, except RTC (if present)
System Reset All functional units, except:
• RTC (if present),
• RCU_STAT,
• RCU_BCODE, and
• the units on the VDDEXT power domain
System Reset All functional units, except:
• RTC (if present),
• RCU_STAT,
• RCU_BCODE, and
• the units on the VDDEXT power domain
Core Only Reset Core n only, for (2 ≥ n ≥ 0)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register or by another functional unit such as the TRU or