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Functional Description
The MMU enables tasks or applications to be written in a way that requires them to have no knowledge of the
physical memory map of the system, or about other programs that might be running simultaneously. This enables
you to use the same virtual memory address space for each program. It also lets you work with a contiguous virtual
memory map, even if the physical memory is fragmented. This virtual address space is separate from the actual phys-
ical map of memory in the system. Applications are written, compiled and linked to run in the virtual memory
space. Virtual addresses are those used by you, and the compiler and linker, when placing code in memory. Physical
addresses are those used by the actual hardware system.
The first level MMU uses a Harvard design with separate micro TLB structures in the PFU for instruction fetches
and in the DPU for data read and write requests. A miss in the micro TLB results in a request to the main unified
TLB shared between the data and instruction sides of the memory system. The TLB consists of a 128-entry two-way
set-associative RAM based structure. The TLB page-walk mechanism supports page descriptors held in the L1 data
cache. The caching of page descriptors is configured globally for each translation table base register, TTBRx, in the
system coprocessor, CP15.
Page table entries support:
• 16 MB super sections
• 1 MB sections
• 64 KB large pages
• 4 KB small pages
Virtual Memory translation tables are typically created by operating systems, and are often dynamically
NOTE:
managed by the memory management layer. However, even a bare metal system can enable the MMU. For
this, a flat mapping technique is used, where all virtual memory addresses shall be programmed exactly
same as the physical memory addresses in the system.
NOTE:
In order to utilize L1-Data Cache, application has to enable the MMU, via Co-Processor 15 in the ARM
Core. After MMU and L1-Data Cache are enabled via CP15: SCTLR, application can disable / enable
cache for individual pages / sections.
L2 Cache
The Level 2 Cache Controller in the ADSP-SC589 is a CoreLink Level 2 Cache Controller (L2C-310) from ARM
and is clocked at SYSCLK speed. The addition of an on-chip secondary cache, also referred to as a Level 2 or L2
cache, is a recognized method of improving the performance of ARM-based systems when significant memory traffic
is generated by the processor. By definition a secondary cache assumes the presence of a Level 1 or primary cache,
closely coupled or internal to the processor. The cache controller is a unified, physically addressed, physically tagged
cache. It includes the following features:
• 256 KB total size
• Lockdown by Line / Way / Master
• Fixed line length of 32 bytes, eight words or 256 bits
2–4
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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