Analog Devices ADSP-SC58 Series Hardware Reference Manual page 792

Table 17-6: ADSP-SC58x UART DMA Channel List (Continued)
DMA ID
DMA34
DMA35
DMA37
DMA38
UART Block Diagram
The UART Block Diagram figure shows a simplified block diagram of one UART module and how it interconnects
to the processor system.
Figure 17-1: UART Block Diagram
UART Architectural Concepts
The following sections provide information about the UART architecture.
Internal Interface
The UART is a DMA-capable peripheral with support for separate transmit and receive DMA master channels. It
operates in either DMA or programmed core modes. The core mode requires software management of the data flow
using either interrupts or polling. The DMA method requires minimal software intervention, as the DMA engine
itself moves the data. The
All UART registers are 32 bits wide and the registers connect to the peripheral MMR bus. Not all MMRs can be
used and unused bits are zero-filled. The UART has three interrupt outputs described as follows.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SEC CONTROLLER
DMA CONTROLLER
(DMA CHANNEL)
MMR ACCESS BUS
P2P
(32-BIT DATA)
(8-BIT DATA)
UART
SET
UART_EMASK
CLEAR
32
8
UARTx_CLOCK UART_STATUS
UARTx_SCR
UARTx_CONTROL
and
UART_RBR UART_THR
DMA Channel Name
UART1_TXDMA
UART1_RXDMA
UART2_TXDMA
UART2_RXDMA
UARTx_THR
TSR
UARTx_TAIP
RSR
UARTx_RBR RX FIFO (8 DEEP)
registers also connect to one of the peripheral DMA buses.
UART Functional Description
Description
UART1 Transmit DMA
UART1 Receive DMA
UART2 Transmit DMA
UART2 Receive DMA
PROCESSOR
UARTxCTS
UARTxTX
UARTxRX
UARTxRTS
17–5