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UART Event Control
indicates a receive buffer threshold level. If the UART_CTL.RFIT bit is cleared, software can safely read two words
out of the
UART_RBR
If the UART_CTL.RFIT bit is set, software can safely read four words. The interrupt request and the
UART_STAT.RFCS bit are cleared when the
below the threshold of two (UART_CTL.RFIT=0) or four (UART_CTL.RFIT=1). Because in DMA mode a sta-
tus service routine may not be permitted to read UART_RBR, this interrupt is only recommended in core mode. In
DMA mode, use this functionality for error recovery only.
The UART module uses the UART_IMSK_SET.EDSSI bit to enable the flow control interrupts. If active, a status
interrupt is generated when the sticky UART_STAT.SCTS bit register is set, indicating that the UART_CTS input
of the transmitter been reasserted. A W1C operation to the UART_STAT.SCTS bit clears the interrupt request.
The UART module uses the UART_IMSK_SET.ETFI bit to enable the transmission finished interrupt. If active,
a status interrupt request is asserted when the UART_STAT.TFI bit is set. The UART_STAT.TFI is the sticky
version of the UART_STAT.TEMT bit, indicating that a byte that started transmission has finished. A W1C opera-
tion to the UART_STAT.TFI bit clears the interrupt request.
Multi-Drop Bus Events
Several status bits and interrupt features in the
dling in multi-drop bus mode. These features include the address (UART_STAT.ADDR) bit, the address sticky
(UART_STAT.ASTKY) bit and the enable address word interrupt (UART_IMSK.EAWI). One of the key features
of the multi-drop bus protocol is its address bit. The address bit signifies to the slaves that the master is transmitting
an address word (all read it) or a data word (only the addressed slave reads its). The UART hardware provides an
efficient method of handling the situation described with the use of UART_STAT.ASTKY bit.
The UART module uses the UART_STAT.ASTKY bit in multi-drop bus mode to indicate when an ad-
NOTE:
dress operation for a peripheral is occurring. The UART_STAT.ASTKY bit is a sticky version of the
UART_STAT.ADDR bit. Hardware sets the bit whenever the UART_STAT.ADDR bit is set. Only soft-
ware clears it with a W1C operation. With the UART_STAT.ASTKY bit set, words are received irrespec-
tive of the mode bit or address bit setting. With the UART_STAT.ASTKY bit cleared, only address words
(mode bit =1) are received and words with mode bit =0 are ignored in MDB mode. This bit does not
affect reception in non-MDB modes. (Words with mode bit =0 are not moved from the
ter to the receive FIFO.)
UART Programming Model
The following sections provide basic procedures for configuring various UART operations.
Detecting Autobaud
Refer to
Autobaud Detection
1. Ensure that the timer is disabled.
17–22
register by the time the UART_STAT.RFCS interrupt occurs.
UART_RBR
UART_STAT
section for more information. The required steps are:
is read enough of times, so that the receive buffer drains
and
UART_IMSK
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers facilitate efficient data han-
UART_RSR
regis-
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