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Receive Buffer Register
The
register buffers the receive data flow through the LP. The receive buffer is a four-location deep FIFO.
LP_RX
In the receive buffer, data is transferred to the core or DMA from the receive FIFO where an internal register does
the packing. This packing register is not software accessible. For more information on LP buffer features and opera-
tions, see the LP functional description.
Figure 15-15: LP_RX Register Diagram
Table 15-9: LP_RX Register Fields
Bit No.
(Access)
31:0
DATA
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
0
DATA[15:0] (R/W)
Receive Buffer
31
0
DATA[31:16] (R/W)
Receive Buffer
Bit Name
Receive Buffer.
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x LP Register Descriptions
6
5
4
3
2
1
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
15–21
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