Analog Devices ADSP-SC58 Series Hardware Reference Manual page 47

Sharc+ processor
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Battery Charging Control Register ........................................................................................................ 27–78
Host High-Speed Return to Normal Register ........................................................................................ 27–79
High-Speed Timeout Register ............................................................................................................... 27–80
Chirp Timeout Register ......................................................................................................................... 27–81
Device Control Register ......................................................................................................................... 27–82
DMA Channel n Address Register ......................................................................................................... 27–84
DMA Channel n Count Register ........................................................................................................... 27–85
DMA Channel n Control Register ......................................................................................................... 27–86
DMA Interrupt Register ........................................................................................................................ 27–89
EP0 Configuration Information Register ............................................................................................... 27–91
EP0 Number of Received Bytes Register ................................................................................................ 27–93
EP0 Configuration and Status (Host) Register ...................................................................................... 27–94
EP0 Configuration and Status (Peripheral) Register .............................................................................. 27–98
EP0 NAK Limit Register ..................................................................................................................... 27–101
EP0 Connection Type Register ............................................................................................................ 27–102
EP0 Configuration Information Register ............................................................................................. 27–103
EP0 Number of Received Bytes Register .............................................................................................. 27–105
EP0 Configuration and Status (Host) Register .................................................................................... 27–106
EP0 Configuration and Status (Peripheral) Register ............................................................................ 27–110
EP0 NAK Limit Register ..................................................................................................................... 27–113
EP0 Connection Type Register ............................................................................................................ 27–114
Endpoint Information Register ............................................................................................................ 27–115
EPn Number of Bytes Received Register .............................................................................................. 27–116
EPn Receive Configuration and Status (Host) Register ........................................................................ 27–117
EPn Receive Configuration and Status (Peripheral) Register ................................................................ 27–122
EPn Receive Polling Interval Register .................................................................................................. 27–127
EPn Receive Maximum Packet Length Register ................................................................................... 27–128
EPn Receive Type Register ................................................................................................................... 27–129
EPn Transmit Configuration and Status (Host) Register ..................................................................... 27–131
EPn Transmit Configuration and Status (Peripheral) Register ............................................................. 27–135
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
xlvii

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