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Each interrupt can be configured as a normal or a secure interrupt. Software force registers and software priority
masking are also supported. The "Register Descriptions" section in this chapter provide brief descriptions of these
ARM-based registers. For complete information refer to the ARM® Generic Interrupt Controller Architecture version
1.0 Architecture Specification.
GIC Functional Description
The GIC splits logically into a GICPORT0 (distributor block) and one GICPORT1 (CPU interface blocks).
General Interrupt Controller Port0 (GIC Distributer)
The distributor block provides a programming interface to perform the following tasks.
• Globally enable the forwarding of interrupts to the CPU interfaces
• Enable or disable each interrupt
• Set the priority level of each interrupt
• Set the target processor list of each interrupt
• Set each peripheral interrupt to be level-sensitive or edge-triggered
• Set each interrupt as either Group 0 or Group 1
• Forward an SGI to one or more target processors
In addition, the Distributor provides:
• Visibility of the state of each interrupt
• A mechanism for software to set or clear the pending state of a peripheral interrupt.
General Interrupt Controller Port1 (GIC CPU)
GICPORT1 (CPU interface) block performs priority masking and preemption handling for a connected processor
in the system. GICPORT1 supports 8 SGIs (software generated interrupts) and 262 SPIs (shared peripheral inter-
rupts).
Each CPU interface provides a programming interface to perform the following tasks.
• Enable signaling of interrupt requests to the processor
• Acknowledge interrupts
• Indicate that interrupt processing is complete
• Set interrupt priority masks for the processor
• Define the preemption policy for the processor
• Determine the highest priority pending interrupt for the processor
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
GIC Overview
7–59
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