Table of Contents
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Look-up Table .......................................................................................................................................... 40–6
Data Mirroring......................................................................................................................................... 40–6
FIFO Status and Data Requests................................................................................................................ 40–7
CRC Operating Modes ................................................................................................................................ 40–8
Data Transfer Modes ................................................................................................................................ 40–8
Memory Scan Compute-and-Compare Mode........................................................................................ 40–9
Memory Scan Data Verify ................................................................................................................... 40–10
Memory Transfer Compute-and-Compare Mode ................................................................................ 40–10
Memory Transfer Data Fill Mode........................................................................................................ 40–10
CRC Event Control ................................................................................................................................... 40–11
Interrupt Signals..................................................................................................................................... 40–11
CRC Programming Model......................................................................................................................... 40–11
CRC Mode Configuration ...................................................................................................................... 40–11
Look-up Table Generation .................................................................................................................. 40–12
Core Driven Memory Scan Compute-and-Compare Mode ................................................................. 40–12
DMA Driven Memory Scan Compute-and-Compare Mode................................................................ 40–14
Core Driven Memory Scan Data Verify Mode ..................................................................................... 40–15
DMA Driven Memory Scan Data Verify Mode ................................................................................... 40–17
Core Driven Memory Transfer Compute-and-Compare Mode ............................................................ 40–18
DMA Driven Memory Transfer Compute-and-Compare Mode .......................................................... 40–20
DMA Driven Memory Transfer Data Fill Mode .................................................................................. 40–21
ADSP-SC58x CRC Register Descriptions ................................................................................................. 40–23
Data Compare Register ......................................................................................................................... 40–24
Control Register .................................................................................................................................... 40–25
Data Word Count Register .................................................................................................................... 40–28
Data Count Capture Register ................................................................................................................ 40–29
Data Word Count Reload Register ........................................................................................................ 40–30
Data FIFO Register ............................................................................................................................... 40–31
Fill Value Register .................................................................................................................................. 40–32
Interrupt Enable Register ...................................................................................................................... 40–33
Interrupt Enable Clear Register ............................................................................................................. 40–34
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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