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Running Priority Register (ICCRPR)
The
GICCPU_RUN_PRIO
interface.
Figure 7-55: GICCPU_RUN_PRIO Register Diagram
Table 7-57: GICCPU_RUN_PRIO Register Fields
Bit No.
(Access)
31:0
VALUE
(R/NW)
ADSP-SC58x GICDST Register Descriptions
GIC Distributor Port (GICDST) contains the following registers.
Table 7-58: ADSP-SC58x GICDST Register List
Name
GICDST_EN
GICDST_SGI_PRIO[n]
GICDST_SPI_PRIO[n]
GICDST_SGI_ACTIVE
GICDST_SGI_CTL
GICDST_SGI_PND_CLR
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register indicates the priority of the highest priority interrupt that is active on the CPU
15
14
0
0
VALUE[15:0] (R)
Run Priority N
31
30
0
0
VALUE[31:16] (R)
Run Priority N
Bit Name
Run Priority N.
The GICCPU_RUN_PRIO.VALUE bit field contains the priority value of the highest
priority interrupt that is active on the CPU interface.
If there is no active interrupt on the CPU interface, and the GIC implements 8-bit
priority fields, a read of this register returns the value 0xFF, corresponding to the low-
est possible interrupt priority. If the GIC implements priority fields of less than 8 bits,
the read might return the register reset value of 0xFF, or might return a value corre-
sponding to the lowest possible interrupt priority. Software cannot determine the num-
ber of implemented priority bits from a read of this register.
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
Description/Enumeration
Description
GIC Port 0 Enable
Software Generated Interrupt Priority Register
Shared Peripheral Interrupt Priority Register
Software Generated Interrupt Active Register
Software Generated Interrupt Control Register
Software Generated Interrupt Clear-Pending Register
ADSP-SC58x GICCPU Register Descriptions
5
4
3
2
1
0
0
0
0
0
0
0
21
20
19
18
17
16
0
0
0
0
0
0
7–87
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