Analog Devices ADSP-SC58 Series Hardware Reference Manual page 925

Functional Description
Table 19-1: ADSP-SC58x PWM Register List (Continued)
Name
PWM_DH_DUTY1
PWM_DL0
PWM_DL0_HP
PWM_DL1
PWM_DL1_HP
PWM_DLYA
PWM_DLYB
PWM_DLYC
PWM_DLYD
PWM_DL_DUTY0
PWM_DL_DUTY1
PWM_ILAT
PWM_IMSK
PWM_STAT
PWM_SYNC_WID
PWM_TM0
PWM_TM1
PWM_TM2
PWM_TM3
PWM_TM4
PWM_TRIPCFG
ADSP-SC58x PWM Interrupt List
Table 19-2: ADSP-SC58x PWM Interrupt List
Interrupt Name
ID
30 PWM0_SYNC
31 PWM0_TRIP
32 PWM1_SYNC
33 PWM1_TRIP
34 PWM2_SYNC
19–4
Description
Channel D-High Full Duty1 Register
Channel D-Low Pulse Duty Register 0
Channel D-Low Heightened-Precision Duty-0 Register
Channel D-Low Pulse Duty Register 1
Channel D-Low Heightened-Precision Duty-1 Register
Channel A Delay Register
Channel B Delay Register
Channel C Delay Register
Channel D Delay Register
Channel D-Low Full Duty0 Register
Channel D-Low Full Duty1 Register
Interrupt Latch Register
Interrupt Mask Register
Status Register
Sync Pulse Width Register
Timer 0 Period Register
Timer 1 Period Register
Timer 2 Period Register
Timer 3 Period Register
Timer 4 Period Register
Trip Configuration Register
Description
PWM0 PWMTMR Grouped
PWM0 Trip
PWM1 PWMTMR Grouped
PWM1 Trip
PWM2 PWMTMR Grouped
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Sensitivity DMA
Channel
Edge
Level
Edge
Level
Edge