Analog Devices ADSP-SC58 Series Hardware Reference Manual page 979

ADSP-SC58x PWM Register Descriptions
Table 19-19: PWM_BCTL Register Fields (Continued)
Bit No.
(Access)
9:8 PULSEMODEHI
(R/W)
2 XOVR
(R/W)
1 DISLO
(R/W)
0 DISHI
(R/W)
19–58
Bit Name
High Side Output Pulse Position.
The PWM_BCTL.PULSEMODEHI bits select the pulse position for Channel B high
side output. In symmetrical mode, the channel forms a symmetrical pulse waveform
around the center of the PWM period. Only one of the duty cycle registers is used for
an output in symmetrical mode. Note that in this mode, the values in the
register is scaled, such that a value of 0 produces 50% duty. In asymmetrical mode, the
channel forms an asymmetrical pulse waveform around the center of the PWM period.
This mode uses both the duty cycle registers
or right half mode, the channel forms the pulse waveforms on either the first half (left)
or the second half (right) of the PWM period. This mode uses both the duty cycle reg-
isters (PWM_BH0
high-low Crossover Enable.
The PWM_BCTL.XOVR bit enables crossover between the channels high and low side
outputs. When enabled, this bit directs the PWM to send the low-side output through
the high-side output pin and the high-side output through the low side output pin.
Channel Low Side Output Disable.
The PWM_BCTL.DISLO bit enables the channels low side output.
Channel High Side Output Disable.
The PWM_BCTL.DISHI bit enables the channels high side output.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
(PWM_BH0
and PWM_BH1).
0 Symmetrical
1 Asymmetrical
2 Left Half
3 Right Half
0 Disable Crossover
1 Enable Crossover
0 Enable Low Side Output
1 Disable Low Side Output
0 Enable High Side Output
1 Disable High Side Output
PWM_BH0
and PWM_BH1). In left half