Analog Devices ADSP-SC58 Series Hardware Reference Manual page 502

Table 11-3: SMC_B0CTL Register Fields (Continued)
Bit No.
(Access)
5:4 MODE
(R/W)
0 EN
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Memory Access Mode.
The SMC_B0CTL.MODE bits select the protocol the SMC uses for static memory
read/write access. Note that the write protocol for async flash, async flash page, and
sync burst flash are all similar; only the read protocols differ for these modes.
Bank 0 Enable.
The SMC_B0CTL.EN bit enables accesses to the memory in bank 0. When this bit is
disabled, accesses to bank 0 return an error response.
ADSP-SC58x SMC Register Descriptions
Description/Enumeration
0 Async SRAM protocol
1 Async flash protocol
2 Async flash page protocol
3 Reserved
0 Disable access
1 Enable access
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