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Control Register
The
register controls DMC modes, DLL calibration, and DRAM initialization.
DMC_CTL
DLLCAL (R0/W)
DLL Calibration Start
PPREF (R/W)
Postpone Refresh
RDTOWR (R/W)
Read-to-Write Cycle
ADDRMODE (R/W)
Addressing (Page/Bank) Mode
RESET (R/W)
Reset SDRAM
PREC (R/W)
Precharge
ZQCL (R0/W)
ZQ Calibration Long
Figure 10-4: DMC_CTL Register Diagram
Table 10-13: DMC_CTL Register Fields
Bit No.
(Access)
25
ZQCL
(R0/W)
24
ZQCS
(R0/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
0
0
0
0
0
0
0
31
30
29
28
27
26
25
0
0
0
0
0
0
0
Bit Name
ZQ Calibration Long.
The DMC_CTL.ZQCL bit starts the ZQ calibration long sequence. Note that this bit
always reads as 0.
ZQ Calibration Short.
The DMC_CTL.ZQCS bit starts the ZQ calibration short sequence. Note that this bit
always reads as 0.
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
Description/Enumeration
0 No effect
1 Triggers ZQ calibration long sequence
0 No effect
1 Triggers ZQ calibration short sequence
ADSP-SC58x DMC Register Descriptions
0
0
DDR3EN (R/W)
DDR3 Mode
LPDDR (R/W)
Low Power DDR Mode
INIT (R0/W)
Initialize DRAM Start
SRREQ (R/W)
Self-Refresh Request
PDREQ (R/W)
Power Down Request
DPDREQ (R/W)
Deep Power-Down Request
16
0
ZQCS (R0/W)
ZQ Calibration Short
10–27
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