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ADSP-SC58x PORT Register Descriptions
Port x GPIO Input Enable Set Register
The
PORT_INEN_SET
register description.
PX15 (R/W1S)
Port x Bit 15 Input Enable Set
PX14 (R/W1S)
Port x Bit 14 Input Enable Set
PX13 (R/W1S)
Port x Bit 13 Input Enable Set
PX12 (R/W1S)
Port x Bit 12 Input Enable Set
PX11 (R/W1S)
Port x Bit 11 Input Enable Set
PX10 (R/W1S)
Port x Bit 10 Input Enable Set
PX9 (R/W1S)
Port x Bit 9 Input Enable Set
PX8 (R/W1S)
Port x Bit 8 Input Enable Set
Figure 14-19: PORT_INEN_SET Register Diagram
Table 14-20: PORT_INEN_SET Register Fields
Bit No.
(Access)
15
PX15
(R/W1S)
14
PX14
(R/W1S)
13
PX13
(R/W1S)
14–54
register enables input drivers for GPIO pins. For more information, see the
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Port x Bit 15 Input Enable Set.
Port x Bit 14 Input Enable Set.
Port x Bit 13 Input Enable Set.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 No Effect
1 Set Bit. Set to enable the input driver.
0 No Effect
1 Set Bit. Set to enable the input driver.
0 No Effect
1 Set Bit. Set to enable the input driver.
1
0
0
0
PX0 (R/W1S)
Port x Bit 0 Input Enable Set
PX1 (R/W1S)
Port x Bit 1 Input Enable Set
PX2 (R/W1S)
Port x Bit 2 Input Enable Set
PX3 (R/W1S)
Port x Bit 3 Input Enable Set
PX4 (R/W1S)
Port x Bit 4 Input Enable Set
PX5 (R/W1S)
Port x Bit 5 Input Enable Set
PX6 (R/W1S)
Port x Bit 6 Input Enable Set
PX7 (R/W1S)
Port x Bit 7 Input Enable Set
17
16
0
0
PORT_INEN
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