Analog Devices ADSP-TS101 TigerSHARC Manuals

Analog Devices ADSP-TS101 TigerSHARC Manuals

Manuals and User Guides for Analog Devices ADSP-TS101 TigerSHARC. We have 1 Analog Devices ADSP-TS101 TigerSHARC manual available for free PDF download: Hardware Reference Manual

Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual (410 pages)

Brand: Analog Devices | Category: Computer Hardware | Size: 10.34 MB

Table of Contents

Table of Contents
3
Preface

19
- Purpose of this Manual
  19
- Intended Audience
  19
- Manual Contents
  20
- Additional Literature
  22
- What's New in this Manual
  22
- Technical or Customer Support
  22
- Processor Family
  23
- Product Information
  23
  - DSP Product Information
    23
  - Product Related Documents
    24
  - Technical Publications Online or on the Web
    24
  - Printed Manuals
    25
    
    Visualdsp++ and Tools Manuals
    25
    
    Data Sheets
    26
    
    Hardware Manuals
    26
  - Recommendations for Improving Our Documents
    26
- Conventions
  27
Introduction

29
- DSP Architecture
  34
  - Compute Blocks
    36
    
    Arithmetic Logic Unit (ALU)
    37
    
    Bit Wise Barrel Shifter (Shifter)
    39
    
    Multiply Accumulator (Multiplier)
    39
  - Integer Arithmetic Logic Unit (IALU)
    40
  - Program Sequencer
    41
    
    Quad Instruction Execution
    42
    
    Context Switching
    43
    
    Nested Call and Interrupt
    43
    
    Relative Addresses for Relocation
    43
  - Internal Memory and Other Internal Peripherals
    44
    
    Internal Buses
    44
    
    Data Accesses
    45
    
    Internal Transfer
    45
    
    Quad Data Access
    45
  - Scalability and Multiprocessing
    46
  - External Port
    47
    
    External Bus and Host Interface
    47
    
    External Memory
    47
    
    Multiprocessing
    48
    
    Host Interface
    49
    
    DMA Controller
    50
    
    Link Ports
    51
  - Miscellaneous
    51
    
    Clock Domains
    51
    
    Timers
    51
- Booting
  52
- Emulation and Test Support
  52
- Programming Model
  53
Memory and Register Map

55
- Memory Access Features
  55
  - Host Address Space
    56
  - External Memory Bank Space
    58
  - Multiprocessor Space
    59
  - Internal Address Space
    60
  - Internal Memory Access
    61
    
    Broadcast Distribution
    62
    
    Broadcast Write
    62
    
    Merged Distribution
    62
  - Data Alignment Buffer
    63
- Register Access Features
  63
  - Register Space
    63
  - Compute Block Register Files
    64
    
    Merged Access
    65
- Broadcast Transfer
  65
- Unmapped Compute Block Registers
  66
- IALU Registers
  68
  - Register J31 - JSTAT
    69
  - Register K31 - KSTAT
    69
- Sequencer Register Groups
  69
- Debug Register Groups
  75
Core Controls

103
- Clock Inputs
  103
- Operation Modes
  104
  - Emulation Mode
    105
  - Supervisor Mode
    106
  - User Mode
    107
- Low Power Mode
  108
  - Entering Low Power Mode
    108
    
    Single Processor System
    108
    
    Multiprocessing Systems
    109
  - Return to Normal Operation
    110
- Flag Pins
  110
- Timers
  111
  - Timer Registers
    111
  - Timer Operations
    111
  - Timer 0 Output Pin
    112
  - Interrupts
    114
- Interrupt I/O Pins
  114
- Interrupt Vector Table
  114
- Interrupt Types
  115
  - Level or Edge Interrupts
    115
- Interrupts Generated by On-Chip Modules
  116
  - Timers
    116
  - Link Interrupts
    117
  - DMA Interrupts
    117
  - Interrupt Pins (IRQ)
    118
  - Vector Interrupt (VIRPT)
    119
  - Bus Lock Interrupt
    119
  - Hardware Error Operations
    120
- Software Exceptions
  121
  - Emulation Debug
    122
- Other Interrupt Registers
  123
  - ILAT Register
    123
  - IMASK Register
    124
  - PMASK Register
    125
- Interrupt Service
  126
  - Interrupt Handling
    131
- Returning from Interrupt
  134
- Exceptions
  135
Cluster Bus

139
- External Bus Features
  140
- Bus Interface I/O Pins
  141
- Processor Microarchitecture
  141
- SYSCON Programming
  149
  - Bus Width
    152
- Control Signals
  154
- Pipelining Transactions
  156
- Wait Cycles
  161
  - Slow Device Protocol
    165
- EPROM Interface
  169
- Flyby Transactions
  172
  - Multiprocessing
    176
  - Bus Arbitration Protocol
    179
    
    Core Priority Access (CPA)
    181
    
    Bus Fairness — BMAX
    185
    
    Host Interface
    186
    
    Backoff
    188
Sdram Interface

197
- SDRAM I/O Pins
  197
- SDRAM Physical Connection
  198
  - Connection
    201
- SDRAM Programming
  209
  - SDRAM Enable
    212
  - Setting the SDRAM Buffering Option (Pipeline Depth)
    213
  - Selecting the SDRAM Page Size (Page Boundary)
    215
  - Setting the SDRAM Power-Up Mode (Init Sequence)
    217
  - Multiprocessing Operation
    218
  - Understanding DQM Operation
    219
  - SDRAM Controller Commands
    220
    
    Precharge (PRE) Command
    221
    
    Terminating Read/Write Cycles
    222
    
    Bank Active (ACT) Command
    223
    
    Read Command
    224
    
    Write Command
    228
  - Refresh (REF) Command
    232
- Programming Example
  233
Direct Memory Access

241
- DMA Controller Features
  241
  - Autodma Transfers
    243
    
    Two-Dimensional DMA
    244
  - Chained DMA
    245
  - DMAR I/O Pins
    246
  - Terminology
    247
- Setting up DMA Transfers
  248
- DMA Transfer Control Block Registers
  249
  - DIX Register
    250
  - DXX Register
    251
  - Dpx Register
    252
- DMA Control and Status Registers
  257
  - DMA Control Registers
    260
    
    DCNTST Register
    262
    
    Type Setup – Links Transmit (Channels 4 to 7)
    263
    
    Type Setup – EP (Channels 0 to 3)
    264
    
    Address Range
    265
  - DMA Controller Operations
    266
    
    Autodma Register Control
    267
    
    DMA Channels
    268
    
    DMA Channel Prioritization
    270
    
    Rotating Priority
    273
  - DMA Chaining
    275
    
    Enabling and Disabling Chaining
    276
    
    Transfer Control Blocks and Chain Loading
    277
    
    Chain Insertion
    278
  - Two-Dimensional DMA
    279
    
    Two-Dimensional DMA Operation
    280
    
    DMA Interrupts
    282
    
    Ending a DMA Sequence
    283
- External Port DMA
  284
  - External Port DMA Transfer Types
    285
    
    Internal to External Memory
    288
    
    External I/O Device to External Memory (Flyby)
    289
    
    External Memory to External I/O Device (Flyby)
    291
    
    DMA Semaphores
    293
    
    Handshake Mode
    295
  - Link Ports DMA
    297
    
    Receiving Link Port to Link Port
    298
  - DMA Throughput
    300
    
    Internal Memory DMA
    301
- DMA Operation on Boot
  302
Link Ports

304
- Link Architecture
  304
  - Transmitting and Receiving Data
    306
Interrupts

309
- Link Port Communication Protocol
  310
- Transmission Delays
  317
- Error Detection Mechanisms
  319
  - Transmitter Error Detection
    320
- Control Register (Lctlx)
  321
- Status Register (Lstatx)
  325
Debug Functionality

330
- Operating Modes
  330
  - Watchpoints
    331
    
    Programming – Control and Address Pointer Registers
    332
    
    Watchpoint Operation
    335
    
    Watchpoint Status (Wpistat)
    336
  - Instruction Address Trace Buffer (TBUF)
    337
- Performance Monitors
  338
  - Cycle Counter (CCNT1–0)
    339
  - Performance Monitor Counter
    340
  - JTAG Instruction Register
    342
System Design

347
- Overview
  347
- Tigersharc Processor Pins
  349
  - Pin Definitions
    350
- Strap Pin Function Descriptions
  353
  - Pin Usage
    354
    
    Pin States at Reset
    356
  - Power, Reset, and Clock Input Considerations
    357
    
    Timer Interrupt and FLAG I/O Examples
    358
  - Clock Description and Jitter
    361
    
    General High Speed Clock Distribution Issues
    362
  - Reset and Boot
    363
    
    Booting
    364
    
    Handling BMS
    365
    
    No Boot Mode
    366
    
    Host Boot
    368
    
    Link Port Boot
    370
    
    Booting a Multiprocessor System
    372
    
    A Single Tigersharc Processor Boots Other Processors
    374
    
    Multiprocessor Host Booting
    376
    
    Memory Initialization During Boot
    377
    
    Multiprocessor Link Port Booting
    378
  - Boot EPROM to Internal Memory
    379
    
    Eprom Tcb
    380
    
    Internal Memory TCB
    381
  - Boot Link to Internal Memory
    382
  - Boot Autodma Register to Internal Memory
    383
- JTAG Issues
  384
  - Signal Integrity
    385
    
    ADSP-TS101 Processor EZ-KIT Lite
    386

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