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Operating Modes
are connected through the pin mux to configurable trigger masters using PWM master IDs
TRGM_SYS_PWMn_SYNC_IN. Using the TRU, these masters can be connected to the PWM_SYNC trigger
slaves in any desired combination.
• A TTU trigger output. This option can include a member of a TTU trigger group, which can also control the
timing of other devices such as ADCs, SINC filter inputs, or GP timers. The TTU supports relative trigger
delays so that timing offsets can be applied to manage system latencies with precision.
• A general-purpose timer trigger master
• A software trigger master. This option allows starting one or more PWM units simultaneously by an MMR
write.
The external PWM_SYNC signal only determines the operation of the main timer PWMTMR0.
Synchronize the external sync by setting the PWM_CTL.EXTSYNCSEL bit to 0 (assumes the external PWM_SYNC
selected is asynchronous).
The external PWM_SYNC period is expected to be an integer multiple of the value of the
When the rising edge of the external PWM_SYNC is detected, the PWMTMR0 timer is restarted at the beginning of
its period. If the external PWM_SYNC period is not exactly an integer multiple of the internal PWM_SYNC, the be-
havior of the PWM channel outputs which are referenced to PWMTMR0 are clipped.
The effect latency from PWM_SYNC_IN to the PWM outputs is about three clock cycles in synchronous mode, and
five clock cycles in asynchronous mode.
CAUTION:
Do not change the value of the PWM_CTL.EXTSYNC bit while the PWM is enabled
(PWM_CTL.GLOBEN =1).
Output Disable and Cross-Over Modes
Each
PWM_ACTL
channel control register contains separate enable bits for the high and low-side signals. The PWM
module uses the PWM_ACTL.DISHI and PWM_ACTL.DISLO bits in the channel A control register to enable or
disable the PWM_AH and PWM_AL outputs respectively. If the disable bit is set (=1), then the corresponding PWM
output is disabled, irrespective of the value of the corresponding duty cycle register. This PWM output signal re-
mains in the OFF state as long as the corresponding enable or disable bit is set.
The cross-over bit (PWM_ACTL.XOVR) allows programs to send the low-side output through the high-side output
pin and the high-side output through the low-side output pin.
One example uses the following configuration:
• The
register =0
PWM_AH0
• The PWM_CHANCFG.MODELSC bit =0
• The PWM_ACTL.DISLO bit =1
• The PWM_ACTL.XOVR bit =1
19–26
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PWM_TM0
period register.
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