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SMC Architectural Concepts
The reset value of turnaround transition time is two cycles. Program the SMC_B0ETIM.TT bit to a value either
greater than or equal to two cycles, depending on memory AC-timing specifications. It is important to be aware that
the SMC_B0ETIM.TT bit is programmed to 0 only when:
• There are either only read accesses or only write accesses possible to external memory devices for the current
device configuration or processor operation situation.
ARDY Input Control
Each bank can be programmed to sample the SMC_ARDY input after the read or write access timer has counted
down. It can also be programmed to ignore this input signal. If enabled and disabled at the sample window, the
SMC module uses SMC_ARDY to extend the access time, as required.
The processor treats SMC_ARDY as an asynchronous input. The input must reach the desired value (either asserted
or deasserted) more than two SCLK0_0 cycles before the completion of access time (scheduled rising edge of
SMC_AWE or SMC_ARE). This timing determines whether the SMC extends the access with the assertion of
SMC_ARDY. After the processor samples SMC_ARDY high, the total delay between SMC_ARDY going high at the
pads and SMC_ARE being deasserted at the pads is a maximum of five SCLK0_0 cycles. (The memory device asserts
SMC_ARDY.)
Asynchronous SRAM writes are also possible with the SMC_ARDY signal enabled. In asynchronous SRAM writes,
the write access is extended beyond the programmed write access cycles depending on the SMC_ARDY signal state.
Once SMC_ARDY is sampled asserted, the SMC_AWE signal is deasserted after two CLKOUT cycles and the write
access ends.
The polarity of SMC_ARDY is programmable on a per-bank basis. Since SMC_ARDY is not sampled until an access
is in-progress to a bank in which the SMC_ARDY enable is asserted, it is not driven by default. When using flash
memory, connect the WAIT input to SMC_ARDY.
To avoid stalls in the case of erroneous SMC_ARDY behavior, set the SMC_B0CTL.RDYABTEN bit to enable the
SMC_ARDY abort counter. When the abort counter is enabled, it starts counting down as soon as the programmed
read/write access cycles expire. If the SMC interface does not sample the SMC_ARDY signal as asserted within 64
cycles, a counter-timeout occurs. This timeout ensures that the processor does not hang if SMC_ARDY is not sam-
pled correctly.
SMC Operating Modes
The SMC supports the following operating modes:
•
Asynchronous Flash Mode
•
Asynchronous Page Mode
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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