Analog Devices ADSP-SC58 Series Hardware Reference Manual page 76

Sharc+ processor
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Serial Data Routing Control Register 1 ................................................................................................. 33–61
Serial Data Routing Control Register 2 ................................................................................................. 33–62
Serial Data Routing Control Register 3 ................................................................................................. 33–63
Serial Data Routing Control Register 4 ................................................................................................. 33–64
Serial Data Routing Control Register 5 ................................................................................................. 33–65
Serial Data Routing Control Register 6 ................................................................................................. 33–66
Frame Sync Routing Control Register 0 ................................................................................................ 33–67
Frame Sync Routing Control Register 1 ................................................................................................ 33–69
Frame Sync Routing Control Register 2 ................................................................................................ 33–71
Frame Sync Routing Control Register 4 ................................................................................................ 33–72
Falling-Edge Interrupt Mask Register .................................................................................................... 33–73
Core Interrupt Priority Assignment Register ......................................................................................... 33–76
Rising-Edge Interrupt Mask Register ..................................................................................................... 33–79
High Priority Interrupt Latch Register .................................................................................................. 33–82
Shadow High Priority Interrupt Latch Register ..................................................................................... 33–85
Low Priority Interrupt Latch Register .................................................................................................... 33–89
Shadow Low Priority Interrupt Latch Register ...................................................................................... 33–92
Miscellaneous Control Register 0 .......................................................................................................... 33–96
Miscellaneous Control Register 1 .......................................................................................................... 33–98
Pin Buffer Enable Register 0 ................................................................................................................ 33–100
Pin Buffer Enable Register 1 ................................................................................................................ 33–101
Pin Buffer Enable Register 2 ................................................................................................................ 33–102
Pin Buffer Enable Register 3 ................................................................................................................ 33–103
Pin Buffer Assignment Register 0 ........................................................................................................ 33–104
Pin Buffer Assignment Register 1 ........................................................................................................ 33–105
Pin Buffer Assignment Register 2 ........................................................................................................ 33–106
Pin Buffer Assignment Register 3 ........................................................................................................ 33–107
Pin Buffer Assignment Register 4 ........................................................................................................ 33–108
Pin Status Register ............................................................................................................................... 33–110
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference

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