Analog Devices ADSP-SC58 Series Hardware Reference Manual page 682

LP Functional Description
multiprocessing schemes. A set of registers governs LP operations. For more information on LP functionality, see the
LP register descriptions.
Table 15-1: ADSP-SC58x LP Register List
Name
LP_CTL
LP_DIV
LP_RX
LP_STAT
LP_TX
LP_TXIN_SHDW
LP_TXOUT_SHDW
ADSP-SC58x LP Interrupt List
Table 15-2: ADSP-SC58x LP Interrupt List
Interrupt Name
ID
77 LP0_DMA
78 LP0_STAT
79 LP1_DMA
80 LP1_STAT
208 LP0_DMA_ERR
209 LP1_DMA_ERR
ADSP-SC58x LP Trigger List
Table 15-3: ADSP-SC58x LP Trigger List Masters
Trigger ID Name
64 LP0_DMA
65 LP1_DMA
Table 15-4: ADSP-SC58x LP Trigger List Slaves
Trigger ID Name
48 LP0_DMA
49 LP1_DMA
15–2
Description
Control Register
Clock Divider Value Register
Receive Buffer Register
Status Register
Transmit Buffer Register
Shadow Input Transmit Buffer Register
Shadow Output Transmit Buffer Register
Description
LP0 DMA Channel
LP0 Status
LP1 DMA Channel
LP1 Status
LP0 DMA Data Error
LP1 DMA Data Error
Description
LP0 DMA Channel
LP1 DMA Channel
Description
LP0 DMA Channel
LP1 DMA Channel
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Sensitivity DMA
Channel
30
36
Sensitivity
Sensitivity
Pulse
Pulse